Intel SA-1100 11.8.13 UDC Status/Interrupt Register

11-76 SA-1100 Developer’s Manual
Peripheral Control Module
11.8.13 UDC Status/Interrupt Register
The UDC status/interrupt register (UDCSR) contains bits that are used to generate the UDC’s
interrupt request. Each bit in the UDC status/interrupt register is logically ORed together to
produce one interrupt request. When the ISR for the UDC is executed, it must read the UDC
status/interrupt register to determine why the interrupt occurred.
Every bit in the UDCSR is controlled by a mask bit in the UDC control register. The mask bits,
when set, will prevent a status bit in the UDCSR from being set. If the mask bit for a particular
status bit is cleared and an interruptible condition occurs, the status bit will be set. In order to clear
status bits, the CPU must write a one into the position that it wishes to clear. The interrupt request
for the UDC will remain active as long as the value of the UDCSR is non-zero.
11.8.13.1 Endpoint 0 Interrupt Request (EIR)
The endpoint 0 interrupt request will be set if the EIM bit in the UDC control register is cleared,
and in the UDC endpoint 0 control/status register, the OUT packet ready bit gets set, the IN packet
ready bit gets cleared, the data end bit gets cleared, the setup end bit gets set, or the sent STALL bit
gets set. The EIR bit is cleared by writing a one to it.
11.8.13.2 Receive Interrupt Request (RIR)
The receive interrupt request bit gets set if the RIM bit in the UDC control register is cleared and
the Receive Packet Complete bit in the UDC endpoint 1 control/status register gets set. The RIR bit
is cleared by writing a one to it.
11.8.13.3 Transmit Interrupt Request (TIR)
The transmit interrupt request bit gets set if the TIM bit in the UDC control register is cleared and
the Transmit Packet Complete bit in the UDC endpoint 2 control/status register gets set. The RIR
bit is cleared by writing a one to it.
11.8.13.4 Suspend Interrupt Request (SUSIR)
The suspend interrupt request bit will be set if the SRM bit in the UDC control register is cleared and
the USB bus remains idle for more than 3 ms. The SUSIR bit gets cleared by writing a one to it.
11.8.13.5 Resume Interrupt Request (RESIR)
The resume interrupt request bit will be set if the SRM bit in the UDC control register is cleared,
the UDC is currently in the suspended state, and the USB bus is driven with resume signalling.