Intel SA-1100 manual Utdr, Ror Fre Pre

Peripheral Control Module

The following table shows the bit locations corresponding to the data field, parity, framing, and receiver overrun error bits within the UART data register. Note that both FIFOs are cleared when the SA-1100 is reset, the transmit FIFO is cleared when writing TXE=0, and the receive FIFO is cleared when writing RXE=0.

Address: 0h 8005 0014						UTDR				Read/Write
Bit	10		9	8	7	6	5	4	3	2	1	0
		ROR	FRE	PRE			Bottom of receive FIFO data
Reset	0		0	0	0	0	0	0	0	0	0	0
						Read Access
			(Note: ROR, FRE, PRE are not read, but rather are transferred to
		corresponding status bits in UTSR1 each time a data value is transferred to UTDR.)
	Bit		7	6	5	4	3	2	1	0
					Top of transmit FIFO data
Reset			0	0	0	0	0	0	0	0
						Write Access
Bit	Name						Description
7..0	DATA		Top/bottom of transmit/receive FIFO data.
			Read – Bottom of receive FIFO data.
			Write – Top of transmit FIFO data.
8	PRE		Parity error.
			0 – No parity errors encountered in the receipt of this data (or parity disabled).
			1 – Parity error encountered in the receipt of this data.
			Note: Each time an 11-bit value reaches the bottom of the receive FIFO, bit 8 from the
			last FIFO entry is transferred to the PRE bit in UTSR1.
9	FRE		Framing error.
			0 – Stop bit for this frame was a one.
			1 – Stop bit for this frame was a zero.
			Note: Each time an 11-bit value reaches the bottom of the receive FIFO, bit 9 from the
			last FIFO entry is transferred to the FRE bit in UTSR1.
10	ROR		Receiver overrun.
			0 – No receiver overrun has been detected.
			1 – Receive logic attempted to place data into receive FIFO while it was full; one or more
			data values following this entry were lost.
			Note: Each time an 11-bit value reaches the bottom of the receive FIFO, bit 10 from the
			last FIFO entry is transferred to the ROR bit in UTSR1.

11-138 SA-1100 Developer’s Manual