Intel SA-1100 manual Framing Error Status FRE read/write, nonmaskable interrupt, HSSR0, Fre

Peripheral Control Module

11.10.10.6 Framing Error Status (FRE) (read/write, nonmaskable interrupt)

The framing error status (FRE) bit is set when a frame alignment error is detected by the receive logic. A frame alignment error is detected on received data when a preamble is followed by something other than another preamble or a start flag.

The following table shows the bit locations corresponding to the status and flag bits within HSSP status register 0. Note that the reset state of all writable status bits is unknown (indicated by question marks) and must be cleared (by writing a one to them) before enabling the HSSP. Also note that writes to reserved bits are ignored and reads return zeros.

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	Address: 0h 8004 0074			HSSR0		Read/Write & Read-Only
Bit	7	6	5	4	3	2	1	0
		Reserved	FRE	RFS	TFS	RAB	TUR	EIF
Reset	0	0	?	0	0	?	?	?

Bit	Name		Description
0	EIF	End/error in FIFO (read-only).
		0	– Bits 8–10 are not set within any of the eight bottom entries of the receive FIFO.
		Receive FIFO DMA service requests are enabled.
		1 – One or more tag bits (8 – 10) are set within one or more of the bottom eight entries of
		the receive FIFO. Request interrupt, disable receive FIFO DMA service requests.
1	TUR	Transmit FIFO underrun.
		0	– Transmit FIFO has not experienced an underrun.
		1	– Transmit logic attempted to fetch data from transmit FIFO while it was empty;
		interrupt request signalled if not masked (if TUS=1).
2	RAB	Receiver abort.
		0	– No abort has been detected for the incoming frame.
		1– Abort detected during receipt of incoming frame. Two or more chips containing no
		pulses (0000) detected on receive pin. EOF bit set in receive FIFO next to last piece of
		“good” data received before the abort, interrupt requested.
3	TFS	Transmit FIFO service request (read-only).
		0	– Transmit FIFO is more than half-full (nine or more entries filled) or transmitter
		disabled.
		1	– Transmit FIFO is half-full or less (eight or fewer entries filled) and transmitter
		operation is enabled. DMA service request signalled; interrupt request signalled if not
		masked (if TIE=1).
4	RFS	Receive FIFO service request (read-only).
		0	– Receive FIFO contains 11 or fewer entries of data or receiver disabled.
		1	– Receive FIFO is two- to three-fifths full (contains 9, 10, 11, or 12 entries of data) or
		more, and receiver operation is enabled. DMA service request signalled; interrupt
		request signalled if not masked (if RIE=1).
5	FRE	Framing error.
		0	– No framing errors encountered in the receipt of this data.
		1	– Framing error occurred; preamble followed by something other than another
		preamble or start flag, request interrupt.
7..6	—	Reserved.

SA-1100 Developer’s Manual 11-123