Intel SA-1100 manual Sdlc Register Definitions, Transmit and Receive FIFOs, 11-84

Peripheral Control Module

11.9.1.11Transmit and Receive FIFOs

To reduce chip size and power consumption, the SDLC’s FIFOs use self-timed logic (they are not clocked). Because of process and environmental variations, the depth at which a service request is triggered to empty the receive FIFO is variable. This variation spans a maximum of four FIFO entries; the receive FIFO service request can be made at four different FIFO depths. To compensate for this variability and guarantee that at least four valid entries of data exist within the FIFO before generating a service request, an extra four entries have been added to the receive FIFO (four entries more than the transmit FIFO). The transmit FIFO is 8 entries deep and the receive FIFO is 12 entries deep. The point at which the receive FIFO service request is triggered spans the middle third of the 12-entry FIFO. The service request is signalled at a depth from one-third full to two-thirds full or when the FIFO contains five, six, seven, or eight entries of data.

This service request variation applies only to an empty FIFO that is filled (receive FIFO). It does not apply to a full FIFO that is emptied (transmit FIFO). The transmit FIFO is guaranteed to signal a service request when it has four or more empty entries and negate the request when the FIFO contains five or more entries that are filled.

If the DMA is used to service either one or both of the SDLC’s FIFOs, the burst size must be set to 4 words, even though more than four entries of data may exist within the receive FIFO. If programmed I/O is used to service the FIFOs, a maximum of 4 words may be added to the transmit FIFO without checking if more space is available. Likewise, a maximum of 4 words may be removed from the receive FIFO without checking if more data is available. After this point, the user must poll a set of status bits that indicate if any data remains in the receive FIFO or if space is available in the transmit FIFO before emptying or filling the FIFOs any further.

11.9.1.12CPU and DMA Register Access Sizes

Bit positioning, byte ordering, and addressing of the SDLC is described in terms of little endian ordering. All SDLC registers are 8 bits wide and are located in the least significant byte of individual words. The ARM peripheral bus does not support byte or half-word operations. All reads and writes of the SDLC by the CPU should be wordwide. Two separate dedicated DMA requests exist for both the transmit and the receive FIFOs. If the DMA controller is used to service the transmit and/or receive FIFOs, the user must ensure that the DMA is properly configured to perform byte-wide accesses, using 4 bytes per burst (half the size of the FIFOs). Note that a separate set of registers also exist to configure UART operation.

See the Section 11.9, “Serial Port 1 – SDLC/UART” on page 11-78for a full description of programming and the operation of serial port 1 as a UART.

11.9.2SDLC Register Definitions

There are eight registers within serial port 1: five control registers, one data register, and two status registers. The control registers are used to select UART or SDLC mode, baud rate, number of start flags, bit modulation mode, and address match value. They are used to select whether an abort or end of frame occurs when the transmit FIFO underruns, whether the sample clock is an input or output, and which edge of the sample clock is used to sample receive data and drive transmit data. Also they are used to enable or disable the FIFO interrupt service request, sample clock input/output operation, aborts after frames, receive operation, transmit operation, receive address matching, and loopback mode. See the Section 11.9, “Serial Port 1 – SDLC/UART” on page 11-78for a full description of UART programming and operation.

The data register addresses the top location of the transmit FIFO and bottom location of the receive FIFO. When it is read, the receive FIFO is accessed, and when it is written, the transmit FIFO is accessed.

11-84 SA-1100 Developer’s Manual