Intel SA-1100 manual Codec Control Register Data Transfer, Bit Audio Data Telecom Data, 11-150

Peripheral Control Module

The width of each entry within the audio and telecom FIFOs is 16 bits. However, the audio codec’s sample/conversion data size is 12 bits and the telecom is 14 bits. Conversions and samples are left justified within the 16-bit audio and telecom data fields in the MCP frame as well as within the transmit and receive FIFOs. Figure 11-34shows the required data alignment for the transmit and receive audio and telecom FIFOs. The user must left justify data to be transmitted, and shift received data to the right before using the results.

Figure 11-34. Audio/Telecom Transmit/Receive FIFO Data Format

Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						Audio Data							0	0	0	0
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							Telecom Data								0	0

To reduce chip size as well as power consumption, the MCP’s FIFOs use self-timed logic (not clocked). Because of process and environmental variations, the depth at which a service request is triggered to empty the receive FIFOs is variable. This variation spans a maximum of four FIFO entries, thus the audio and telecom receive FIFO service requests can be made at four different FIFO depths.To compensate for this variability and guarantee that at least four valid entries of data exist within either FIFO before generating a service request, an extra four entries have been added to both receive FIFOs (four entries more than the transmit FIFOs). Thus the audio and telecom transmit FIFOs are 8-entries deep and the audio and telecom receive FIFOs are 12-entries deep. The point at which the receive FIFO service requests are triggered spans one-third (four entries) of the 12-entry FIFOs. The service request is signalled at a depth from one-third full to two-thirds full (when the FIFOs contains five, six, seven, or eight entries of data).

11.12.1.4Codec Control Register Data Transfer

The UCB1100 and UCB1200 contain sixteen 16-bit registers used to configure the chip, and store touch-screen and ADC samples as well as digital I/O pin state and edge interrupt status. These registers are read and written via the MCP’s serial interface using three fields that exist within the MCP’s data frame. In Figure 11-31, bits 15:0 contain the value read from or written to the off-chip codec, bits 46:43 contain the register address of the current read or write, and bit 42 is used by the MCP to signal a read or write cycle to the codec. These fields are configured by the CPU by writing to MCP control register 2, and are then transmitted to the off-chip codec. These fields are also received every data frame by the MCP from the codec and are placed in MCP control register 2, which can be read by the CPU. Note that the contents of the addressed register are returned in the receive data frame regardless of the state of the read/write bit. Thus for write cycles, both a write and a read occurs, and for read cycles, only a read occurs.

A register write is performed by writing a value to the MCP control register 2 that contains the value to store to the register, the address of the register, and the read/write bit set to one. Once this register is written, its contents are transferred to the correct fields within the serial shifter on the next rising edge of the SFRM signal. The register information is transmitted to the UCB1100 or UCB1200 during subframe 0, and the value is written to the selected codec register at the end of subframe 0 (during the 65th bit of the frame). The control register value and address are also returned to the MCP and stored in MCP control register 2. The read/write bit is zero in the return frame. Because the addressed register is updated at the end of subframe 0, the data returned during the frame in which the write occurred represents the previous contents of the register. The updated value is returned during the next data frame.

11-150 SA-1100 Developer’s Manual