Intel SA-1100 Hssp Register Definitions, Hssp Control Register, IrDA Transmission Rate ITR, Lpm

Peripheral Control Module

Bit	Name		Description
0	HSE	HP-SIR enable.
		0	– HP-SIR modulation disabled; ICP functions as normal UART if ITR=0.
		1	– HP-SIR modulation enabled; ICP functions as low-speed IrDA port if ITR=0.
1	LPM	Low-power mode.
		0	– Each zero encoded as a pulse that is 3/16 of the programmed bit time if ITR=0.
		1	– Each zero encoded as a pulse that is 1.6 µs wide if ITR=0.
7..2	—	Reserved.

11.10.5HSSP Register Definitions

There are six registers within the HSSP: three control registers, one data register, and two status registers. The control registers are used to select IrDA transmission rate, address match value, whether an abort or end of frame occurs when the transmit FIFO underruns, and true or complemented transmit and receive data; to enable or disable transmit and receive operation, the FIFO interrupt service requests, receive address matching, and loopback mode.

The data register addresses the top location of the transmit FIFO and bottom location of the receive FIFO. When it is read, the receive FIFO is accessed, and when it is written, the transmit FIFO is accessed.

The status registers contain bits that signal CRC, overrun, underrun, framing, and receiver abort errors as well as the transmit FIFO service request, receive FIFO service request, and end-of-frame conditions. Each of these hardware-detected events signals an interrupt request to the interrupt controller. The status registers also contain flags for transmitter busy, receiver synchronized, receive FIFO not empty, and transmit FIFO not full (no interrupt generated).

11.10.6HSSP Control Register 0

The HSSP control register 0 (HSCR0) contains eight different bit fields that control various functions for 4 Mbps IrDA transmission.

11.10.6.1IrDA Transmission Rate (ITR)

The IrDA transmission rate (ITR) bit is used to select the transmission speed of the ICP. ITR selects the correct type of IrDA bit modulation to use (HP-SIR or 4PPM), and enables the correct serial-to-parallel engine (UART or HSSP). When ITR=0, the HP-SIR modulator is enabled along with serial port 2’s UART. When ITR=1, the 4PPM modulator is enabled as well as the HSSP. Note that ITR is the only control bit that affects both the UART and HSSP. Once one of the two speeds is selected, all further programming is controlled by the individual units (UART or HSSP).

11.10.6.2Loopback Mode (LBM)

The loopback mode (LBM) bit is used to enable and disable the ability of the HSSP’s transmit and receive logic to communicate. When LBM=0, the HSSP operates normally. The transmit and receive data paths are independent and communicate via their respective pins. When LBM=1, the output of the transmit serial shifter is directly connected to the input of the receive serial shifter internally, and control of the TXD2 and RXD2 pins is given to the peripheral pin control (PPC) unit. Note that even though the IrDA standard permits only half-duplex operation, the HSSP does not restrict the user from transmitting and receiving data at the same time; both are fully independent units. This function is essential when using the HSSP in loopback mode.

11-112 SA-1100 Developer’s Manual