Intel SA-1100 manual Telecom Sample Rate Divisor TSD

Peripheral Control Module

Once enabled, the MCP’s audio sample rate clock decrements at the programmed frequency with a 50% duty cycle. The action outlined in the above first bullet item causes the MCP’s audio transmit FIFO logic to transfer the next available value to the audio data field within the serial shifter. Each time the audio sample rate clock decrements to zero, it is reloaded with its programmed ASD modulus value, triggers the audio transmit FIFO logic to transfer the next available value to the audio data field within the serial shifter, and continues to decrement. The MCP’s audio sample rate clock is automatically disabled when:

•A codec control register write to the audio control register B is made (address=0b100), which clears both the audio codec input and output enable bits (bit 14 = aud_in_ena, bit 15 = aud_out_ena), followed by

•The rising edge of the next SFRM pulse after the write has been made.

The resultant audio sample clock rate, given a specific ASD value, can be calculated using the following equation, where ASD is the decimal equivalent of the binary value programmed within the bit field. Note that ASD must be programmed with a value of 6 or larger. Unpredictable results occur for ASD values smaller than 6. Note that one of three clock frequencies can be selected. The first two frequencies are internal clocks selected by the CFS bit in MCCR1 and the third frequency is a user-defined clock that is input via GPIO pin 21 and is divided as defined by the ECP bit field described in following sections.

12×106 SampleRate = -----------------------

32xASD

Valid ASD values are from 6 (00000110) to 127 (11111111)

Note: The 12x106 value within the formula’s numerator should be replaced with the frequency of the clock driven to GPIO pin 21 when an off-chip clock source is used to drive the MCP.

11.12.3.2Telecom Sample Rate Divisor (TSD)

The 7-bit telecom sample rate divisor (TSD) bit field is used to synchronize the MCP with the sample rate of the telecom codec. The telecom sample rate clock is required for the same reason and works exactly like the audio sample rate clock, except for one minor difference. The valid TSD values range from 16 to 127 (instead of 6), allowing a total of 112 different audio sample rates to be selected, ranging from a minimum of 2.358 K samples per second using the 9.585-MHz internal clock to a maximum of 23.400 K samples per second using the 11.98-MHz internal clock. Note that slower sample rates can be achieved using an externally supplied clock.

The resultant telecom sample clock rate, given a specific TSD value, can be calculated using the following equation, where TSD is the decimal equivalent of the binary value programmed within the bit field. Note that TSD must be programmed with a value of 16 or larger. Unpredictable results occur for TSD values smaller than 16. Note that one of three clock frequencies can be selected. Thr first two frequencies are internal clocks selected by the CFS bit in MCCR1 and the third frequency is a user-defined clock that is input via GPIO pin 21 and is divided by the ECP bit field described in the following sections.

12×106 SampleRate = -----------------------

32xTSD

Valid TSD values are from 16 (00010000) to 127 (11111111)

Note: The 12x106 value within the formula’s numerator should be replaced with the frequency of the clock driven to GPIO pin 21 when an off-chip clock source is used to drive the MCP.

SA-1100 Developer’s Manual 11-153