Intel SA-1100 10-8 SA-1100

10-8 SA-1100 Developer’s Manual
Memory and PCMCIA Control Module
31..17 DRI<14:0> DRAM refresh interval.
The number of memory clock cycles (divided by 4) between CAS bef ore RAS (CBR)
refresh cycles. One row is refreshed in each DRAM bank during eac h CBR refresh
cycle.
The value that must be loaded into this register is calculated as follows:
DRI = Number of cycles/4 = ((Refresh time / rows) - (longest burst access time)) x
Mem clock frequency /4.
The longest burst access time to subtract must also take into consideration access to
ROM or Flash EPROM. (These may be interrupted to service a DRAM refresh cycle
after each 32-bit word. If there is a read on a 16-bit bus, a refresh cycle may be
inserted after 2 read cycles. If there is a read to a 32-bit bus, the refresh waits one
read cycle to be serviced. The DRAM interface inserts CBR refresh cycles between
bursts of up to 8 words. Because the address pins are ignored by the DRAMs during
CBR refresh cycles, PCMCIA transactions may be ongoing during a refresh cycle and
will not be interrupted.)
Bit Name Description