SA-1100 Developer’s Manual iii
Contents
1 Introduction.................................................................................................................. ....1-1
1.1 Intel® StrongARM® SA-1100 Microprocessor .................................................. 1-1
1.2 Overview.......................................................................................... .................. 1-4
1.3 Example System........................................................................ ...... ..................1-5
1.4 ARM™ Architecture................................................ ........................................... 1-6
1.4.1 26-Bit Mode .......................................................................................... 1-6
1.4.2 Coprocessors........................................................................................ 1-6
1.4.3 Memory Management................................................................ ...........1-6
1.4.4 Instruction Cache....................................................................... ...........1-6
1.4.5 Data Cache...................................................................................... ..... 1-6
1.4.6 Write Buffer......................................................................... ..................1-7
1.4.7 Read Buffer........................................................................................... 1-7
2 Functional Description.................................................................. ...... ....... ...... ................2-1
2.1 Block Diagram ................................................................................................... 2-1
2.2 Inputs/Outputs ................................................................................................... 2-3
2.3 Signal Description...................................................................... ........................ 2-4
2.4 Memory Map.................................................................................... ..................2-7
3 ARM™ Implementation Options...................................................................... ....... ...... ...3-1
3.1 Big and Little Endian........................................................... ...............................3-1
3.2 Exceptions....................... .................................................................................. 3-1
3.2.1 Power-Up Reset ................................................................................... 3-2
3.2.2 ROM Size Select .................................................................................. 3-2
3.2.3 Abort......................... ............................................................................ 3-3
3.2.4 Vector Summary........................................ ........................................... 3-4
3.2.5 Exception Priorities.................................... ........................................... 3-4
3.2.6 Interrupt Latencies and Enable Timing...... ........................................... 3-5
3.3 Coprocessors..................................................................................................... 3-5
4 Instruction Set ....... .......................................................................................................... 4-1
4.1 Instruction Set............................................................................ ........................4-1
4.2 Instruction Timings............................................................................................. 4-1
5 Coprocessors..................... ............................................................................................. 5-1
5.1 Internal Coprocessor Instructions.............. ........................................................ 5-1
5.2 Coprocessor 15 Definition ................................................................................. 5-2
5.2.1 Register 0 – ID.................................................................... ..................5-2
5.2.2 Register 1 – Control................................................................... ...........5-3
5.2.3 Register 2 – Translation Table Base ................................................... 5-4
5.2.4 Register 3 – Domain Access Control......................................... ...........5-4
5.2.5 Register 4 – RESERVED...................................................................... 5-4
5.2.6 Register 5 – Fault Status ...................................................................... 5-4
5.2.7 Register 6 – Fault Address ................................................................... 5-4
5.2.8 Register 7 – Cache Control Operations..................................... ...........5-5
5.2.9 Register 8 – TLB Operations ................................................................ 5-5
5.2.10 Register 9 – Read-Buffer Operations ................................................... 5-6