Intel SA-1100 manual 11-30

Peripheral Control Module

Thus two 16-bit values are packed into each word in the frame buffer. Each 16-bit value is transferred via the DMA from off-chip memory to the input FIFO. Unlike 4- and 8-bit per pixel modes, the 16-bit value bypasses both the palette and the dither logic, and is placed directly in the output FIFO to be output on the LCD’s data pins. Increasing the size of the pixel representation allows a total of 64K colors to be generated. This 16-bit value output to the pins can be organized into one of three RGB color formats: 6 bits of red, 5 bits of green, and 5 bits of blue data; 5 bits of red, 6 bits of green, and 5 bits of blue data; 5 bits of red, 5 bits of green, and 6 bits of blue data, as specified by the user. Note that the pin timing of the LCD changes when active mode is selected. Timing of each pin is described in subsequent bit-field sections for both passive and active mode. Additionally, the LCD controller can be configured in active color display mode and used with an external DAC and optionally an external palette to drive a video monitor. Note that only monitors that implement the RGB data format can be used; the LCD controller does not support the NTSC standard.

Figure 11-9shows which bits within each frame buffer entry (for 16-bit/pixel mode) and which bits within a selected palette entry (for 4- and 8-bit/pixel mode) are sent to the individual LCD data pins. In active mode, GPIO pins 2..9 are also used. Note that the user must configure GPIO pins 2..5 as outputs (for 4- and 8-bit/pixel mode), and GPIO pins 2..9 as outputs (for 16-bit/pixel mode) by setting the appropriate bits within the GPIO pin direction register (GPDR) and GPIO alternate function register (GAFR). See the General-Purpose I/O section for configuration information. If GPDR<6:9> = GAFR<6:9> = 4’hF in 4- or 8-bit/pixel mode, then GPIO<6:9> are pulled low during LCD operation in active mode. However, the user is free to clear GAFR<6:9>, allowing the GPIO unit to assume control of these pins to be used as normal digital I/Os. In general, the user may clear any number of GAFR bits 2..9, to allow the GPIO unit to assume control of unused GPIO pins for normal digital I/O depending on the required number of data pins.

If the panel that is being controlled contains more data pin inputs than 16, the user may still use the SA-1100’s LCD controller, but the panel will be limited to a total of 64 K colors. If the user wishes to maintain the panel’s full range of colors and increase the granularity of the spectrum, the LCD’s 16 data pins should be interfaced to the panel’s most significant R, G, and B pixel data input pins and the least significant R, G, and B data pins should be tied either high or low. If instead, the user wishes to maintain the granularity of the spectrum and limit the overall range of colors possible, the LCD’s 16 data pins should be interfaced to the panel’s least significant R, G, and B pixel data input pins and the most significant data pins should again be tied either high or low.

Figure 11-9. Frame Buffer/Palette Bits Output to LCD Data Pins in Active Mode

16-Bit/Pixel Mode

Frame Buffer Entry

R<5>

R<4>

R<3>

R<2>

R<1>

R<0>

G<4>

G<3>

G<2>

G<1>

G<0>

B<4>

B<3>

B<2>

B<1>

B<0>

R<4>

R<3>

R<2>

R<1>

R<0>

G<5>

G<4>

G<3>

G<2>

G<1>

G<0>

B<4>

B<3>

B<2>

B<1>

B<0>

R<4>

R<3>

R<2>

R<1>

R<0>

G<4>

G<3>

G<2>

G<1>

G<0>

B<5>

B<4>

B<3>

B<2>

B<1>

B<0>

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Data

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

LDD

LDD

LDD

LDD

LDD

LDD

LDD

LDD

Pin

<9>

<8>

<7>

<6>

<5>

<4>

<3>

<2>

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

4- or 8-Bit/Pixel Mode

Selected Palette Entry

R<3>

R<2>

R<1>

R<0>

G<3>

G<2>

G<1>

G<0>

B<3>

B<2>

B<1>

B<0>

VSS1

Bit

VSS

VSS

VSS

11

10

9

8

7

6

5

4

3

2

1

0

Data

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

LDD

LDD

LDD

LDD

LDD

LDD

LDD

LDD

Pin

<9>

<8>

<7>

<6>

<5>

<4>

<3>

<2>

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

1GPIO pins 6..0 are grounded by the LCD in this mode. However, if GAFR bit 6..9 are cleared within the system control module, these pins can be used as normal GPIO pins.

11-30 SA-1100 Developer’s Manual