Intel SA-1100 manual UDC Control Register

Peripheral Control Module

11.8.3UDC Control Register

The UDC control register (UDCR) contains seven control bits: two to enable or disable the UDC and five to mask the transmit and receive FIFO service requests.

11.8.3.1UDC Disable (UDD)

The UDC disable (UDD) bit is used to enable and disable the UDC. When UDD=0, the UDC is enabled for serial transmission or reception. When UDC=1, it is disabled and the UDC+ and UDC- pins are tristated.

If UDD is written to one the entire UDC design is reset. If this is done while the UDC is actively transmitting or receiving data, it stops immediately and the remaining bits within the transmit or receive serial shifter are reset. In addition, all entries within the transmit and receive FIFO ar reset.

11.8.3.2UDC Active (UDA)

This read-only bit can be read to determine if the UDC is currently active. A one indicates that the UDC is currently involved in a transaction.

11.8.3.3Bit 2 Reserved

Bit 2 is reserved and should always be written to a zero to ensure compatibility with future revisions of this design. This bit also will be set if the UDC detects that the data toggle mechanism did not occur.

11.8.3.4Endpoint 0 Interrupt Mask (EIM)

The endpoint 0 interrupt mask (EIM) bit is used to mask or enable the endpoint 0 interrupt request. When EIM=1, the interrupt is masked and the EIR bit in the status/interrupt register is not allowed to be set. When EIM=0, the interrupt is enabled, and whenever an interruptible condition occurs in the receiver, the EIR bit is set. Note that programming EIM=1 does not affect the current state of EIR; it only blocks future zero to one transitions of EIR.

11.8.3.5Receive Interrupt Mask (RIM)

The receive interrupt mask (RIM) bit is used to mask or enable the receive FIFO service request interrupt. When RIM=1, the interrupt is masked and the RIR bit in the status/interrupt register is not allowed to be set. When RIM=0, the interrupt is enabled, and whenever an interruptible condition occurs in the receiver, the RIR bit is set. Note that programming RIM=1 does not affect the current state of RIR; it only blocks future zero to one transitions of RIR.

11.8.3.6Transmit Interrupt Mask (TIM)

The transmit interrupt mask (TIM) bit is used to mask or enable the transmit endpoint 2 interrupt request. When TIM=1, the interrupt is masked and the TIR bit in the status/interrupt register is not allowed to be set. When TIM=0, the interrupt is enabled, and whenever an interruptible condition occurs in the transmitter, the TIR bit is set. Note that programming TIM=1 does not affect the current state of TIR; it only blocks future zero to one transitions of TIR.

11-64 SA-1100 Developer’s Manual