Intel SA-1100 Caches, Write Buffer, and Read Buffer, Instruction Cache Icache, Icache Operation

Caches, Write Buffer, and Read Buffer 6

To reduce effective memory access time, the Intel® StrongARM® SA-1100 Microprocessor (SA-1100) has an instruction cache, a data cache, a write buffer, and a read buffer. All except the read buffer are transparent to program execution. The following sections describe each of these units and give all necessary programming information.

6.1Instruction Cache (Icache)

The SA-1100 contains a 16 Kbyte instruction cache (Icache). The Icache has 512 lines of 32 bytes (8 words), arranged as a 32-way set associative cache, and uses the virtual addresses generated by the processor core. The Icache is always reloaded a line at a time (8 words). It may be enabled or disabled via the SA-1100 control register, and is disabled on the assertion of nRESET or through a software or sleep reset sequence. (See Section 9, “System Control Module” on page 9-1in the System Control Module for details.) The operation of the cache, when memory management is enabled, is further controlled by the cacheable or C bit stored in the memory-management page table. If memory management is disabled, all addresses are marked as cacheable (C=1). When memory management is enabled, the C bit in each page table entry can disable caching for an area of virtual memory.

6.1.1Icache Operation

In the SA-1100, the instruction cache is searched regardless of the state of the C bit; only reads that miss the cache are affected. If, on an Icache miss, the C bit is a one or the Memory Management Unit (MMU) is disabled, a linefetch of 8 words is performed and it is placed in a cache bank with a round-robin replacement algorithm. If, on a miss, the MMU is enabled and the C bit is a zero for the given virtual address, an external memory access for a single word is performed and the cache is not written.The Icache should be enabled as soon as possible after reset for best performance.

6.1.2Icache Validity

The Icache operates with virtual addresses, so care must be taken to ensure that its contents remain consistent with the virtual-to-physical mappings performed by the memory management unit. If the memory mappings are changed, the Icache validity must be ensured. The Icache is not coherent with stores to memory, so programs that write cacheable instruction locations must ensure the Icache validity. Instruction fetches do not check the write buffer, so data must not only be pushed out of the cache but the write buffer must also be drained.

6.1.2.1Software Icache Flush

The entire Icache can be invalidated by writing to the SA-1100 cache operations register (register 7). The cache is flushed immediately when the register is written, but note that the following instruction fetches may come from the cache before the register is written.

SA-1100 Developer’s Manual 6-1