Intel SA-1100 manual Dram Burst-of-Eight Transactions

Memory and PCMCIA Control Module

Figure 10-4shows the rate of the shift registers during DRAM nCAS timing for burst-of-eight transactions.

Figure 10-4. DRAM Burst-of-Eight Transactions

Memory Clock

nRAS

TRP

nCAS

ADDR ROW COL COL+4 COL+8 COL+12 COL+16 COL+20 COL+24 COL+28

Reads:

nOE

Input Data D0 D1D2D3D4D5D6D7

Latch Input Data (internal):

Writes:
nWE
Write Data
		D0	D1	D2	D3	D4	D5	D6	D7
Contents of DRAM register fields:					last		time			first
MDCAS1 = 11 0001	1000 1100 (binary)		MDCAS0 = 0110 0011 0001 1000 1100 0110 0000 0111 (binary)
MDCNFG:TRP = 4	MDCNFG:CDB2 = 1			TDL = 00

A4778-01

Contents of DRAM register fields:	time
last		first

MDCAS1=11 0001 1000 1100(binary) MDCAS0= 0110 0011 0001 1000 1100 0110 0000 0111(binary)

MDCNFG:TRP=4 MDCNFG:CDB2=1 TDL=00

SA-1100 Developer’s Manual 10-17