Intel SA-1100 manual Multimedia Communications Port Enable MCE, External Clock Select ECS, 11-154

Peripheral Control Module

11.12.3.3Multimedia Communications Port Enable (MCE)

The MCP enable (MCE) bit is used to enable and disable all MCP operation. Since the MCP and SSP both share the same pins, only one can be enabled at a time. If the user enables both at the same time, the MCP has precedence and the SSP remains disabled. However, both can be enabled when the SSP pin reassignment (SPR) bit within the PPC unit is set, which assigns the SSP to GPIO pins. See the following sections for a description of the SSP enable (SSE) bit.

When the MCP is disabled, all of its clocks are powered down to minimize power consumption. If the SSP is also disabled, the TXD4, RXD4, SCLK, and SFRM pins can be used for general-purpose input/output. See the Section 11.13, “Peripheral Pin Controller (PPC)” on

page 11-184for a description of how to program the PPC unit to reassign the SSP’s pins and to use serial port 4’s pins as I/Os. Note that MCE and CFS are the only control bits within the MCP that are reset to a known state. MCE is cleared to zero to ensure the MCP is disabled following a reset of the SA-1100.

When the MCP is enabled, SCLK begins to transition and the start of the first frame is signalled by pulsing the SFRM pin high for one SCLK period. The rising edge of SFRM coincides with the rising edge of SCLK. As long as the MCE bit is set, the MCP operates continuously, transmitting and receiving 128 bit data frames. When the MCE bit is cleared, the MCP is disabled immediately, causing the current frame, which is being transmitted, to be terminated and control of serial port 4’s pins to be given to the PPC unit. Clearing MCE resets the MCP’s FIFOs. However, MCP data register 3, the control, and the status registers are not reset. The user must ensure these registers are properly reconfigured before reenabling the MCP.

11.12.3.4External Clock Select (ECS)

The external clock select (ECS) bit selects whether one of the two on-chip clocks derived by the 3.6864-MHz oscillator is used by the MCP or if an off-chip clock is supplied via GPIO pin 21. When ECS=0, the MCP can be programmed to select one of two frequencies: either 9.585 MHz or 11.981 MHz. This clock is also used to increment the audio and telecom sample rate counters. (See preceding sections.) When ECS=1, the MCP uses GPIO<21> to input a clock supplied from off-chip. The frequency of the off-chip clock after being scaled by the ECP bit field can be any value within the allowable frequency range of the UCB100 up to 12 MHz. This off-chip clock is useful when a sample rate frequency, which is not a multiple of 9.585 MHz or 11.981 MHz is required for synchronization with either the audio and/or telecom portion of the UCB1100 or UCB1200 codecs. When using GPIO pin 21 for the input clock, the user must also set bit 21 of the GPIO alternate function register (GAFR) and clear bit 21 of the GPIO pin direction register (GPDR). See the Section 9.1, “General-Purpose I/O” on page 9-1 .

11.12.3.5A/D Sampling Mode (ADM)

The A/D sampling mode (ADM) bit selects whether the MCP takes audio and telecom data from the incoming frame only when their respective data valid bits are set or whenever the MCP’s audio and telecom sample rate counters time-out, indicating that the data in the next incoming frame is valid. When ADM=0, data is taken from the incoming frame and is placed into the audio or telecom FIFO whenever the incoming audio or telecom data valid bit is set. When ADM=1, after the MCP is enabled, data is taken from the incoming frame when the data valid bit is set for the first time. After this point, the data valid bit is ignored, and samples are stored each time the audio or telecom sample rate counters decrement to zero, indicating that a new A-to-D sample was taken and will be available in the next frame.

The UCB1100 and UCB1200 have two different modes of operation to control the setting of the audio and telecom data valid bits. In one mode, the codec only sets the data valid bit when a new A-to-D sample is contained within the incoming data frame. Once the data is transmitted to the

11-154 SA-1100 Developer’s Manual