Intel SA-1100 manual ROM Interface Overview, ROM Timing Diagrams and Parameters

Memory and PCMCIA Control Module

The RT fields in the MSCx registers specify the type of memory (burst-of-four ROM, burst-of-eight ROM, nonburst ROM, Flash, SRAM) and the RBW fields specify the bus width for the memory space selected by nCS<3:0>. If a 16-bit bus width is specified, transactions take place across data pins D<15:0>.

10.4.1ROM Interface Overview

The SA-1100 provides programmable timing for both burst and nonburst ROMs. The RDF field in MSCx is the latency (in memory clock cycles) for nonburst ROMs and the first data beat of a burst ROM. RDN is the latency for the burst data beats after the first for burst ROMs. RRR delays the following access to a different memory space to allow time for the current ROM to tristate the data bus. This parameter should be programmed with the maximum tOFF value, as specified by the ROM manufacturer. One memory clock cycle is added to each of these parameters. At power-on reset, the SMCNFG0 field in the MSC0 register is initialized such that the RDF, RDN, and RRR fields are set to their maximum values to accommodate the slowest ROMs at initial boot; RT is set to be nonburst ROM; and RBW0 is loaded with the value of the inverse of the ROM_SEL pin. The remaining fields in MSC0 and MSC1 are not initialized on power-on reset. MSC0:SMCNFG0 is selected when the address space corresponding to nCS0 is accessed.

The SA-1100 supports a ROM burst size of 1, 4, or 8 words. A single DRAM CBR refresh cycle may be inserted between word accesses within a transaction. nCS and nOE are deasserted during the refresh cycle.

10.4.2ROM Timing Diagrams and Parameters

Figure 10-6, Figure 10-7, and Figure 10-8show the timing for burst and nonburst ROMS.

SA-1100 Developer’s Manual 10-19