Memory and PCMCIA Control Module

Figure 10-14. PCMCIA Voltage-Control Logic

Intel®

StrongARM®*

SA-1100

D<15:0>

nCS<3> nOE

 

Socket x

2

BVD 1,2

 

2

VSS 1,2

 

EN#

 

Transparent

 

Latch

 

VPPEN

 

3VEN

Voltage-Control

5VEN

Circuit

 

WR

 

nWE

* StrongARM is a registered trademark of ARM Limited.

A6845-01

The PCMCIA card voltage may be controlled through a set of discrete registers mapped into a static chip select. For example, Figure 10-14shows mapping to chip select 3.

10.6.3PCMCIA Interface Timing Diagrams and Parameters

Figure 10-15shows a 16-bit access to a 16-bit memory or I/O device. The parameter, BS, is programmed in the MECR register. When common memory is accessed, the MECR:BSM1 or MECR:BSM2 field is used, depending on whether card socket 0 or 1 is addressed. MECR:BSIO1(2) is used for I/O accesses and MECR:BSA1(2) is used for access to attribute memory. Figure 10-15and Figure 10-16show the appropriate setting of BS_xx = 0b00001.

SA-1100 Developer’s Manual

10-31

Page 145
Image 145
Intel SA-1100 manual Pcmcia Interface Timing Diagrams and Parameters, Pcmcia Voltage-Control Logic