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Intel SA-1100 manual 0h 9006, HSCR2, Rxp Txp

Models: SA-1100

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Peripheral Control Module

The following table shows the location of the bits within HSSP control register 2. Both bits are set to one to ensure serial port 2’s pins default to normal “true” data operation following a reset of the SA-1100. Note that the HSSP and UART must be disabled (RXE=TXE=0) when changing the state of these bits. Also note that reads of reserved bits return zero and writes have no effect.

	Address:		0h 9006 0028			HSCR2			Read/Write
Bit	23		22	21	20	19		18	17		16

			Reserved				RXP	TXP		Reserved

Reset	0		0	0	0	1		1	0		0

Bit	Name		Description

17..16	—	Reserved.

18	TXP	Transmit pin polarity select.
		0	– Data output from the HSSP, UART, or PPC is first inverted before being output to TXD2.
		1	– Data output from the HSSP, UART, or PPC to TXD2 is true or non-inverted data.

19	RXP	Receive pin polarity select.
		0	– Data input from RXD2 is first inverted before being used by the HSSP, UART, or PPC.
		1	– Data input from RXD2 to the HSSP, UART, or PPC is true or non-inverted data.

23..20	—	Reserved.

11-118

SA-1100 Developer’s Manual

Image 268

Intel SA-1100 manual 0h 9006, HSCR2, Rxp Txp

Contents

Intel StrongARM SA-1100 Microprocessor Developer’s ManualSA-1100 Developer’s Manual Contents Caches, Write Buffer, and Read Buffer Memory-Management Unit MMU1.6 System Control ModuleReviving the DRAMs from Self-Refresh Mode Memory and Pcmcia Control ModulePeripheral Control Module 11-39 11.8.3.4Endpoint 0 Interrupt Mask EIM 11-64 11.8.3.5Receive 11-81 SA-1100 Developer’s Manual 11-128 Serial Port 4 MCP / SSP 11-169 11.12.12.1Transmit Fifo Not Full Flag TNF KHz Oscillator Specifications Register Summary MHz Oscillator SpecificationsInternal Test Figures SA-1100 Power and Clock Supply Sources and States Tables14-4 Page Introduction Intel StrongARM SA-1100 MicroprocessorLCD DMAFeatures of the SA-1100 CPU for AA and EA Parts Features of the SA-1100 CPU for CA and DA PartsAdditional Features Built into SA-1100 Chipset Changes to the SA-1100 Core from the SA-110Overview Example System SA-1100 Example SystemARM Architecture Write Buffer Read BufferPage Block Diagram Functional DescriptionSA-1100 Block Diagram Inputs/Outputs Signal Descriptions Sheet 1 Signal DescriptionName Type Description Signal Descriptions Sheet 2 Signal Descriptions Sheet 3 TDO OCZVDD VSSMemory Map 1GB Pcmcia Interface Mbyte Static Memory ROM, Flash, SramBig and Little Endian ARM Implementation OptionsExceptions Power-Up Reset ROM Size SelectAbort Address Exception Mode on Entry Vector SummaryException Priorities Vector SummaryInterrupt Latencies and Enable Timing CoprocessorsPage Instruction Group Result Delay Issue Cycles Instruction SetInstruction Set Instruction TimingsPage Coprocessors Internal Coprocessor InstructionsCoprocessor 15 Definition Register 0 IDCache and MMU Control Registers Coprocessor Register Register Reads Register WritesRegister 1 Control Register 3 Domain Access Control Register 5 Fault StatusRegister 6 Fault Address Register 2 Translation Table BaseRegister 7 Cache Control Operations Register 8 TLB OperationsFunction OPC2Register 9 Read-Buffer Operations Registers 10 12 ReservedRegister 13 Process ID Virtual Address Mapping Access process ID register 0b000 0b0000CRm Register 14 Debug Support Breakpoints Dbcr Bit ActionRegister 15 Test, Clock, and Idle Control 0b010 0b0100 Wait for interrupt 0b1000Page Caches, Write Buffer, and Read Buffer Instruction Cache IcacheIcache Operation Icache ValidityIcache Enable/Disable and Reset Data Caches DcachesEnabling the Icache Disabling the IcacheCacheable Bit C Bufferable Bit BCacheable Reads C = Noncacheable Reads C =Software Dcache Flush Dcaches Enable/Disable and ResetDoubly Mapped Space Bufferable Bit Write Buffer WBWrite Buffer Operation Read Buffer RB Enabling the Write BufferWrites to a Bufferable and Noncacheable Location B=1,C=0 Unbufferable Writes B=0Caches, Write Buffer, and Read Buffer Page MMU Faults and CPU Aborts Memory-Management Unit MMUData Aborts MMU RegistersInteraction of the MMU, Icache, Dcache, and Write Buffer Cacheable Reads LinefetchesBuffered Writes Valid MMU, Dcache, and Write Buffer CombinationsTo disable the MMU Mini Data CachePage Clocks SA-1100 Crystal OscillatorsRTC ARMCore Clock Configuration Register Restrictions on Changing the Core Clock ConfigurationCore Clock Configurations CCF40 Core Clock Frequency in MHz MHz Crystal OscillatorDriving SA-1100 Crystal Pins from an External Source Clocking During Test System Control Module General-Purpose I/OGpio Register Definitions Gpio Pin Edge DetectGpio Pin-Level Register Gplr Bit Name DescriptionBit Reset Gpio Pin Direction Register GpdrPS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 Bit Name Description Gpio Falling-Edge Detect Register Grer Bit Name Description Gpio Rising-Edge Detect Register Grer31..28 Reserved Gpio Edge Detect Status Register Gedr Gpio Alternate Function Register Gafr Pin Alternate Function Direction Unit Signal Description Gpio Alternate FunctionsGpio Register Locations Address Name DescriptionInterrupt Controller Interrupt Controller Register DefinitionsInterrupt Bits InterruptBit Position Unit Source Module Interrupt Controller Pending Register IcprBit Field Description IP9 IP8 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 IMn Interrupt mask n where n = 0 through Interrupt Controller Mask Register IcmrInterrupt Controller Level Register Iclr Bit NameDisable idle mask Idle mode. This bit is cleared during all resetsInterrupt Controller Control Register Iccr DIMInterrupt Controller Register Locations Real-Time ClockRTC Counter Register Rcnr RTC Alarm Register Rtar RTC Status Register RtsrALE HZERTC Trim Register Rttr Trim ProcedureOscillator Frequency Calibration Rttr Value Calculations Trim Example #1 Measured Value Has No Fractional ComponentOperating System Timer Real-Time Clock Register LocationsOS Timer Count Register Oscr OS Timer Match Registers 0-3 OSMR0, OSMR1, OSMR2, OSMR3OS Timer Watchdog Match Enable Register Ower WMEOS Timer Status Register Ossr Watchdog Timer OS Timer Interrupt Enable Register OierInterrupt enable channel OS Timer Register Locations OS Timer Register LocationsPower Manager Run ModeIdle Mode Entering Idle ModeSleep Mode Exiting Idle ModeCPU Preparation for Sleep Mode Events Causing Entry into Sleep ModeSleep Shutdown Sequence During Sleep ModeSleep Wake-Up Sequence Booting After Sleep Mode Assumed Behavior of an SA-1100 System in Sleep Mode Reviving the DRAMs from Self-Refresh ModeRUN Hardware ResetIdle Sleep Pin State During Step Pin Operation in Sleep ModePin Name Type Power Manager Registers Power Manager Control Register PmcrPower Manager General Configuration Register Pcfr OpdePower Manager PLL Configuration Register Ppcr Power Manager Wake-Up Enable Register Pwer WEnBFS Power Manager Sleep Status Register PssrVFS Bit is cleared. This bit is cleared on hardware reset Dram control holdPeripheral control hold 31..5 ReservedPower Manager Scratch Pad Register Pspr Power Manager Gpio Sleep State Register PgsrPower Manager Oscillator Status Register Posr Power Manager Register LocationsPower Manager Register Locations Reset Controller Hardware resetReset Controller Registers Reset Controller Software Reset Register RsrrSoftware reset SWRReset Controller Status Register Rcsr Reset Controller Register LocationsReset Controller Register Locations Page Memory and Pcmcia Control Module Overview of OperationIntel SA-1100 Memory Controller InterfaceMemory and Pcmcia Control Module 10-2Example Memory Configuration Example Memory SystemTypes of Memory Accesses ReadsWrites Transaction SummaryRead-Lock-Write Aborts and Nonexistent MemorySA-1100 Transactions Bus OperationPhysical Address Symbol Register Name Memory Configuration RegistersMemory Interface Control Registers Dram Configuration Register Mdcnfg CDB231..17 DRI140 Dram refresh interval CycleMem clock frequency /4 Will not be interruptedDram CAS Waveform Shift Registers MDCAS0, MDCAS1, MDCAS2 ROM or the first access of a burst ROM For Flash and SRAM, this determines the read access timeStatic Memory Control Registers MSC1-0 One memory clock cycle is added to this valueAccesses of a burst ROM 12..8 RDNx40 ROM delay next accessFor Flash and SRAM, this determines the write pulse width Expansion Memory Pcmcia Configuration Register Mecr BSxx Bit Encoding Bclk Speeds for 160-MHz Processor Core FrequencyBclksel Bclk Cycle Time-nsDynamic Interface Operation Dram OverviewDram Memory Size Options Dram Row/Column Address MultiplexingDram Timing Addr Mdcnfgtrp = 4 MDCNFGCDB2 =Dram Burst-of-Eight Transactions Dram Self-Refresh in Sleep Mode Static Memory InterfaceDram Refresh 10-18ROM Timing Diagrams and Parameters ROM Interface OverviewA255 A42Input Data Latch 10-20Eight Beat Burst Read from Burst-of-Four ROM SA-1100 Developer’s ManualSram Write Timing Diagram 4-Beat Burst Sram Timing Diagrams and ParametersSram Interface Overview Flash Eprom Interface Overview Flash Eprom Timing Diagrams and Parameters 10-24Static Access Followed by a Dram Access Dram Access Followed by a Static AccessDram Access Followed by a Refresh Operation General Memory BUS TimingPcmcia Overview 10-2610.6.1 32-Bit Data Bus Operation AddressExternal Logic for Pcmcia Implementation 10-2812. Pcmcia External Logic for a Two-Socket Configuration 13. Pcmcia External Logic for a One-Socket Configuration 10-30Pcmcia Interface Timing Diagrams and Parameters 14. Pcmcia Voltage-Control Logic15. Pcmcia Memory or I/O 16-Bit Access 10-3216. Pcmcia I/O 16-Bit Access to 8-Bit Device Initialization of the Memory Interface Flow of Events After Reset or Exiting Sleep Mode10-34 Alternate Memory Bus Master Mode Page Peripheral Control Module Read/Write InterfaceMemory Organization Peripheral Register Width DMA Burst SizePeripheral Units’ Base Addresses Peripheral Serial Protocol Base AddressLCD Controller 0h B010 Serial Port ICP HsspInterrupts Peripheral Units’ Interrupt NumbersInterrupt PeripheralDedicated Peripheral Pins Peripheral PinsPeripheral Gpio Pin Function Use of the Gpio Pins for Alternate Functions Peripheral Unit Gpio Pin AssignmentDMA Controller DMA Register DefinitionsDMA Device Address Register DDARn Controller From Half-word wide D31 D0 1 0 from memoryDevice From To Half-word wide To From Byte-wide Ddar Fields Unit Name Function Address DA318 DS30 Valid Settings for the DDARn Register11-10 DMA Control/Status Register DCSRn DMA Buffer a Start Address Register DBSAn DMA Buffer a Transfer Count Register DBTAnDMA Operation DMA Buffer B Start Address Register DBSBnDMA Buffer B Transfer Count Register DBTBn TCB120 Transfer count buffer BPhysical Address Register Name Symbol DMA Register ListDBSA3 DBTA3DBSB3 DBTB3LCD Controller 11-16Lpclk LCD Controller Operation DMA to Memory InterfaceFrame Buffer 11-18PBS 13..12 Pixel bit sizeTo palette Frame to paletteUnused Red Data30 Green Data30 Blue Data30 Encoded Pixel Data70 BitEncoded Pixel Data150 FrameBufferSize = 32 + 16 + è 11-22Input Fifo Lookup PaletteColor/Gray-Scale Dithering Output FifoColor/Gray-Scale Intensities and Modulation Rates Dither Value Intensity Modulation RateLCD Controller Pins LCD Controller Register DefinitionsLCD Enable LEN LCD Controller Control RegisterColor/Monochrome Select CMS Single-/Dual-Panel Select SDSLCD Controller Data Pin Utilization Single Passive Screen Portion PinsDual Panel Active Panel LCD Data-Pin Pixel Ordering 11-28LCD Disable Done Interrupt Mask LDM Base Address Update Interrupt Mask BAMError Interrupt Mask ERM Passive/Active Display Select PAS11-30 Palette DMA Request Delay PDD Double-Pixel Data DPD Pin Mode11.7.3.8 Big/Little Endian Select BLE LEN CMSSDS LDMPAS BLEDPD PDDPixels Per Line PPL Horizontal Sync Pulse Width HSWEnd-of-Line Pixel Clock Wait Count ELW 11-34Beginning-of-Line Pixel Clock Wait Count BLW PPLHSW ELWVertical Sync Pulse Width VSW Lines Per Panel LPP11-36 End-of-Frame Line Clock Wait Count EFW Beginning-of-Frame Line Clock Wait Count BFWLPP VSWEFW BFWPixel Clock Divider PCD AC Bias Pin Frequency ACBAC Bias Pin Transitions Per Interrupt API Vertical Sync Polarity VSPHorizontal Sync Polarity HSP Pixel Clock Polarity PCPOutput Enable Polarity OEP Address 0h B010LCD Controller DMA Registers HSPPCP OEPDMA Channel 1 Base Address Register 31..0DBAR1 DMA channel 1 base address pointerDMA Channel 1 Current Address Register DCAR1DMA channel 1 current address pointer Equal to the calculated end address of the bufferDMA Channel 2 Base and Current Address Registers DBAR2DCAR2 DMA channel 2 current address pointerLCD Disable Done Flag LDD read/write, maskable interrupt Base Address Update Flag BAU read-only, maskable interruptBus Error Status BER read/write, maskable interrupt LCD Controller Status RegisterAC Bias Count Status ABC read/write, nonmaskable interrupt LDD BAUBER ABCIOL IULLCD Controller Register Locations LCD Controller Control, DMA, and Status Register LocationsLCD Controller Pin Timing Diagrams LDDx0LDDx0 Lfclk Llclk Lpclk11-52 12. Passive Mode Pixel Clock and Data Pin Timing DPD =13. Active Mode Timing 11-5414. Active Mode Pixel Clock and Data Pin Timing USB Operation Serial Port 0 USB Device Controller11-56 Signalling Levels 10. USB Bus StatesBus State UDC+/UDC- Pin Levels PortBit Value Digital Data Nrzi Data Bit Encoding11-58 Field Formats 11. Endpoint Field AddressingEndpoint Field Value UDC Endpoint Selected EndpointPacket Formats PIDCRC5 CRC16Transaction Formats ActionOUT Packets from UDC to host are boldfaceSetup DATA0 UDC Device RequestsAction Token Packet Data Packet 11-6212. Host Device Request Summary UDC Register DefinitionsRequest Name UDC Control Register Reset Interrupt Mask REM Suspend/Resume Interrupt Mask SRMAddress 0h 8000 UdccrUDC Address Register UDC OUT Max Packet RegisterUdcar UdcompAddress 0h 8000 000C UDC in Max Packet RegisterUdcimp UDC Endpoint 0 Control/Status Register Serviced Setup End SSE UDCCS0SSE FST SST IPR OPR SSEReceive Fifo Service RFS Receive Packet Error RPEUDC Endpoint 1 Control/Status Register Receive Packet Complete RPCBits 7..6 Reserved UDCCS1RNE FST SST RPE RPC RFS RNETransmit Fifo Service TFS Transmit Packet Error TPEUDC Endpoint 2 Control/Status Register Transmit Packet Complete TPCUDCCS2 FST SST TUR TPE TPC TFSUDC Endpoint 0 Data Register UDC Endpoint 0 Write Count RegisterUDCD0 DataUDC Data Register UddrTop/bottom of transmit/receive Fifo data Read Bottom of receive Fifo dataUDC Status/Interrupt Register Reset Interrupt Request Rstir UdcsrRstir Resir Susir TIR RIR EIR RstirUDC Register Locations Serial Port 1 SDLC/UART13. UDC Control, Data, and Status Register Locations Sdlc Operation Frame Format Address FieldControl Field CRC-CCITTCRC Field Data FieldBaud Rate Generation Receive Operation 11-82Transmit Operation Simultaneous Use of the Uart and SdlcCPU and DMA Register Access Sizes Sdlc Register DefinitionsTransmit and Receive FIFOs 11-84Loopback Mode LBM Sdlc Control RegisterSDLC/UART Select SUS Single/Double Flag Select SDFSample Clock Enable SCE Bit Modulation Select BMSSample Clock Direction SCD 11-86Receive Clock Edge Select RCE Transmit Clock Edge Select TCEAddress 0h 8002 SDCR0Abort After Frame AAF TCETransmit Enable TXE Receive Enable RXEReceive Fifo Interrupt Enable RIE Transmit Fifo Interrupt Enable TIEAddress Match Enable AME Receiver Abort Interrupt EnableRAETransmit Fifo Underrun Select TUS 11-90SDCR1 Read/WriteRAE TUS AME TIE RIE RXE TXE AAF RAESDCR2 Address Match Value AMVAMV Sdlc Control Registers 3 Baud Rate Divisor BRDAddress 0h 8002 006C SDCR3Sdlc Data Register 11-94Address 0h 0078 SddrROR CRE EOF RORSdlc Status Register Transmit Underrun Status TUR read/write, maskable interruptReceiver Abort Status RAB read/write, maskable interrupt 11-96SA-1100 Developer’s Manual 11-97 SDSR0 RFS TFS RAB TUR EIFReceiver Synchronized Flag RSY read-only, noninterruptible Transmitter Busy Flag TBY read-only, noninterruptibleReceive Fifo Not Empty Flag RNE read-only, noninterruptible Transmit Fifo Not Full Flag TNF read-only, noninterruptibleReceiver Overrun Status ROR read-only, noninterruptible CRC Error Status CRE read-only, noninterruptible11-100 SDSR1 ROR CRE EOF RTD TNF RNERSY TBYUart Register Locations 14. Uart Control, Data, and Status Register LocationsSdlc Register Locations Serial Port 2 Infrared Communications Port ICP15. Sdlc Control, Data, and Status Register Locations Low-Speed ICP Operation HP-SIR*ModulationUart Frame Format 11-10411.10.2.1 4PPM Modulation High-Speed ICP OperationChip Timeslots Data = Hssp Frame Format SA-1100 Developer’s Manual 11-107 11-108 SA-1100 Developer’s Manual 11-109 11-110 HP-SIR Enable HSE Low-Power Mode LPMUart Register Definition Uart Control RegisterHssp Register Definitions Hssp Control RegisterIrDA Transmission Rate ITR LPMSA-1100 Developer’s Manual 11-113 11-114 HSCR0 Address 0h 8004AME TIM RIM RXE TXE TUS LBM ITR Search for the next preamble HSCR111-116 Transmit Pin Polarity Select TXP Receive Pin Polarity Select RXP0h 9006 HSCR2RXP TXP RXPHssp Data Register Address 0h 8004 006C HsdrLast Fifo entry is transferred to the ROR bit HSSR1Hssp Status Register Receiver Abort Status RAB read/write, nonmaskable interrupt11-122 Framing Error Status FRE read/write, nonmaskable interrupt HSSR0FRE RFS TFS RAB TUR EIF FREEnd-of-Frame Flag EOF read-only, noninterruptible 11-124SA-1100 Developer’s Manual 11-125 HSSR1 ROR CRE EOF TNF RNE TBY RSY16. Uart Control, Data, and Status Register Locations Hssp Register Locations17. Hssp Control, Data, and Status Register Locations Serial Port 3 Uart Uart OperationLSB MSB 11-12830. NRZ Bit Encoding Example 0100 11-130 Uart Register Definitions Parity Enable PE11.11.3.2 Odd/Even Parity Select OES Data Size Select DSS Stop Bit Select SBS11-132 UTCR0 TCE RCE SCE DSS SBS OESBit Reset BRD70 Uart Control Registers 1UTCR1 UTCR2Transmitter Enable TXE Receiver Enable RXEBreak BRK UTCR3 LBM TIE RIE BRK TXE RXEUart Data Register Utdr ROR FRE PREUart Status Register Receiver Idle Status RID read/write, maskable interrupt Error in Fifo Flag EIF read-only, nonmaskable interrupt11-140 UTSR0 Address 0h 8005 001CEIF REB RBB RID RFS TFS Parity Error Flag PRE read-only, noninterruptible 11-142Framing Error Flag FRE read-only, noninterruptible Receiver Overrun Flag ROR read-only, noninterruptibleRead-Only UTSR1ROR FRE PRE TNF RNE TBY Serial Port 4 MCP / SSP MCP Operation 11-14631. MCP Frame Data Format Audio and Telecom Sample Rates and Data Transfer 11-148MCP Transmit and Receive Fifo Operation Bit Audio Data Telecom Data Codec Control Register Data Transfer11-150 External Clock Operation Alternate SSP Pin AssignmentMCP Register Definitions MCP Control RegisterAudio Sample Rate Divisor ASD 11-152Telecom Sample Rate Divisor TSD Multimedia Communications Port Enable MCE 11.12.3.5 A/D Sampling Mode ADMExternal Clock Select ECS 11-154Telecom Transmit Fifo Interrupt Enable TTE Telecom Receive Fifo Interrupt Enable TREAudio Transmit Fifo Interrupt Enable ATE Audio Receive Fifo Interrupt Enable areExternal Clock Prescaler ECP ASDAudio sample rate divisor TSDMCE ECSADM TTEClock Frequency Select CFS MCP Data RegistersCFS MCP Data Register Address 0h 8006 MCP Data Register 0 MCDR0 Read/WriteReserved for future enhancements 15..4Address 0h 8006 000C MCP Data Register 1 MCDR1 Read/Write SA-1100 Developer’s Manual 11-161 Reg Address R/W Reset Bit Address 0h 8006 MCP Data Register 2 MCDR2 Read/Write15..0 Codec Register read Read/write Read Returns a zeroMCP Status Register 11-164 SA-1100 Developer’s Manual 11-165 Audio Codec Enabled Flag ACE read-only, noninterruptible Telecom Codec Enabled Flag TCE read-only, noninterruptibleCodec Write Completed Flag CWC read-only, noninterruptible Codec Read Completed Flag CRC read-only, noninterruptibleATS ARSTTS TRSTTU TROANF ANESSP Operation 35. Texas Instruments* Synchronous Serial Frame Format 11-17036. Motorola* SPI Frame Format 37. National Microwire* Frame Format 11-172SSP Transmit and Receive FIFOs Bit Bit DataSSP Control Register SSP Register Definitions11-174 Synchronous Serial Port Enable SSE Frame Format FRFFRF Serial Clock Rate SCRSCR Serial Clock Polarity SPO Serial Clock Phase SPH Sclk SPO=0 Sclk SPO=1 Sfrm TXD4 RXD4LSB 11-178SPO Address 0h 8007 006C SSP Data RegisterJustifies data and zero fills unused bits 11-180 SSP Status Register SSP Busy Flag BSY read-only, noninterruptibleBSY MCP Register Locations SSP Register Locations19. MCP Control, Data, and Status Register Locations 20. SSP Control, Data, and Status Register LocationsPPC Operation Peripheral Pin Controller PPC11-184 PPC Register Definitions PPC Pin Direction RegisterSclk PPC Pin State Register Address 0h 9006 Ppsr PPC Pin StateRegister Read/WriteLCD pixel clock pin state Read Current state of LCD pixel clock pin returnedLCD line clock pin state Read Current state of LCD line clock pin returnedPPC Pin Assignment Register Uart Pin Reassignment UPRSSP Pin Reassignment SPR UPRPPC Sleep Mode Pin Direction Register 11-190LCD pixel clock sleep mode pin direction LCD pixel clock pin configured as input during sleepLCD line clock sleep mode pin direction LCD line clock pin configured as input during sleepPPC Pin Flag Register PPC Register Locations 21. PPC Control and Flag Register LocationsPage Symbol Parameter Min Max Units DC ParametersAbsolute Maximum Ratings SA-1100 DC Maximum RatingsSymbol Parameter Min Nom Max Units DC Operating ConditionsSA-1100 DC Operating Conditions × VddxPower Supply Voltages and Currents Parameter SA-1100 UnitsVDD VddxPage Test Conditions AC ParametersSA-1100 Output Derating Memory Bus and Pcmcia Signal Timings Module ConsiderationsMemory Bus Memory Bus Out 13-2MCP Signals LCD Controller SignalsLLDD70 fall Pin Name Symbol Parameter Min Max Unit Timing ParametersSA-1100 AC Timing Table for AA and BA Parts SfrmcAsynchronous Signal Timing Descriptions Page Package and Pinout Mechanical Data and Packaging InformationSA-1100 Pinout 208-Pin Quad Flat Pack 14-2Mini-Ball Grid Array mBGA SA-1100 256 Mini-Ball Grid Array Mechanical DrawingSA-1100 Pinout 256-Pin Mini-Ball Grid Array 14-4Instruction Breakpoint Debug SupportData Breakpoint Page Test Access Port TAP Controller State Transitions Boundary-Scan Test InterfaceReset Pull-Up ResistorsInstruction Register Public InstructionsSAMPLE/PRELOAD ExtestClamp Highz IdcodeBypass 16-4Test Data Registers Bypass Register16.6.3 SA-1100 Boundary-Scan BS Register 16.6.2 SA-1100 Device Identification ID Code Register16-6 Boundary-Scan Interface Signals Tbscl TbschTbsis Tbsih Tbsoh Tbsod Data Tbsss Tbssh Data Out Tbsdh TbsddTbsoe Data Out TbsdeTbsr Tbsrs TbsrhSymbol Parameter Minimum Typical Maximum Units SA-1100 Boundary-Scan Interface TimingPage Register Summary Tucr B000 0044 DMA control/status register 2 write ones to setB000 0048 Write ones to clear 004C Read only 0050 B000 0054Ucdomp Sdlc Registers Serial Port 8002 80318003 Reserved 8003 001C 8004 007C 0h 8004 Ffff Reserved8007 0078 0h 8007 Ffff Reserved PPC Registers 9006 Uart Registers Serial Port 80059006 0034 0h 9006 Ffff Reserved Specifications MHz Oscillator Specifications BSystem Specifications MHz Oscillator Specifications Specification Minimum Typical Maximum UnitSpecification Quartz Crystal SpecificationTypical Maximum Unit Page KHz Oscillator Specifications C Temperature RangeCurrent Consumption Startup TimeFrequency Shift Due to Temperature Effect on the Circuit Parasitic Capacitance Off-chip Between Txtal and TextalParasitic Resistance Between Txtal and Textal Parasitic Resistance Between Txtal or Textal and VSSOther providers supply a Quality Factor, Q, instead of Rm Therefore, the values for QCorresponding to specified range of Rm are supplied Following tableKHz Oscillator Specifications Test Unit Control Register Tucr Internal TestPMD TSEL2-0 TSEL2 TSEL1 TSEL0Page Support, Products, and Documentation