Intel SA-1100 manual SSP Transmit and Receive FIFOs, Bit Bit Data

Peripheral Control Module

11.12.7.2Baud Rate Generation

The baud or bit rate is derived by dividing down the 3.6864-MHz clock generated by the on-chip PLL. The clock is first divided by a fixed value of 2 and then by a programmable number between 1 and 256. This programmability provides a range of transmission rates ranging from 7.2 Kbps to 1.8432 Mbps. The resultant clock is used to drive the SCLK pin and by the transmit and receive logic’s serial shifters to drive and latch data, respectively.

11.12.7.3SSP Transmit and Receive FIFOs

To reduce chip size as well as power consumption, the SSP’s FIFOs use self-timed logic (they are not clocked). Because of process and environmental variations, the depth at which a service request is triggered to empty the receive FIFO is variable. This variation spans a maximum of four FIFO entries, thus the receive FIFO service request can be made at four different FIFO depths. To compensate for this variability and guarantee that at least four valid entries of data exist within the FIFO before generating a service request, an extra four entries have been added to the receive FIFO (four entries more than the transmit FIFO). Thus the transmit FIFO is 8 entries deep and the receive FIFO is 12 entries deep. The point at which the receive FIFO service request is triggered spans one-third (four entries) of the 12-entry FIFO. The service request is signalled at a depth from one-third full to two-thirds full (when the FIFO contains five, six, seven, or eight entries of data).

This service request variation only applies to an empty FIFO that is filled (receive FIFO). It does not apply to a full FIFO that is emptied (transmit FIFO). Thus the transmit FIFO is guaranteed to signal a service request when it has four or more empty entries and negate the request when the FIFO contains five or more entries that are filled.

If the DMA is used to service either one or both of the SSP’s FIFOs, the burst size must be set to four half-words, even though more than four entries of data may exist within the receive FIFO. If programmed I/O is used to service the FIFOs, a maximum of four words may be added to the transmit FIFO without checking if more space is available. Likewise, a maximum of four words may be removed from the receive FIFO without checking if more data is available. After this point, the user must poll a set of status bits, which indicates if any data remains in the receive FIFO or if space is available in the transmit FIFO, before emptying or filling the FIFOs any further.

The width of each entry within the FIFOs is 16 bits. However, the SSP supports data sizes of 4 through 16 bits. Any data that is less than 16-bits wide must be left-justified when writing or DMAing data to the transmit FIFO. Likewise, data received by the SSP is left-justified when it is placed within the receive FIFO. Figure 11-38shows the required data alignment for the transmit and receive FIFOs. The user must left-justify data to be transmitted, and shift received data to the right before using the results.

Figure 11-38. Transmit/Receive FIFO Data Format

Bit	15	14	13	12	11	10	9	8		7	6	5	4	3	2	1	0
		4-Bit Data			0	0	0		0	0	0	0	0	0	0	0	0
			5-Bit Data			0	0		0	0	0	0	0	0	0	0	0
								..
								15-Bit Data									0

16-bit Data

SA-1100 Developer’s Manual 11-173