Intel SA-1100 Hssp Status Register, Receiver Abort Status RAB read/write, nonmaskable interrupt

Peripheral Control Module

11.10.10 HSSP Status Register 0

HSSP status register 0 (HSSR0) contains bits that signal the transmit FIFO service request, receive FIFO service request, receiver abort, transmit FIFO underrun, framing error, and the end/error in receive FIFO conditions. Each of these hardware-detected events signal an interrupt request to the interrupt controller.

A bit that can cause an interrupt signals the interrupt request as long as the bit is set. Once the bit is cleared, the interrupt is cleared. Read/write bits are called status bits; read-only bits are called flags. Status bits are referred to as “sticky” (once set by hardware, must be cleared by software). Writing a one to a sticky status bit clears it; writing a zero has no effect. Read-only flags are set and cleared by hardware; writes have no effect. Additionally, some bits that cause interrupts have corresponding mask bits in the control registers and are indicated in the following sections. Note that the user has the ability to mask all HSSP interrupts by clearing bit 16 within the interrupt controller mask register (ICMR).

11.10.10.1 End/Error in FIFO Status (EIF) (read-only, nonmaskable interrupt)

The end/error in FIFO flag (EIF) is a read-only bit that is set when any tag bits (8 through 10) are set within the bottom eight entries of the receive FIFO and is cleared when no tag bits are set within the bottom eight entries of the FIFO. When EIF is set, an interrupt is signalled and DMA requests to empty the receive FIFO are disabled until EIF is cleared. To discover which FIFO entry contains the end-of-frame or an error condition, the user should check the state of the EOF, CRE, and ROR bits (described in the following sections), then read the corresponding value from the HSDR. This procedure should be repeated until EIF is cleared because set flag bits that are present within any of the eight lowest entries in the receive FIFO can set EIF. Once all tags are cleared from the bottom eight entries of the receive FIFO, EIF is automatically cleared, which in turn, clears the interrupt and reenables receive FIFO DMA requests.

11.10.10.2 Transmit Underrun Status (TUR) (read/write, maskable interrupt)

The transmit underrun status bit (TUR) is set when the transmit logic attempts to fetch data from the transmit FIFO after it has been completely emptied. When an underrun occurs, the transmitter takes one of two actions. When the transmit underrun select bit is clear (TUS=0), the transmitter ends the frame by shifting out the CRC that is calculated continuously on outgoing data, followed by a stop flag and SIP pulse. When TUS=1, the transmitter is forced to transmit an abort and continues to transmit chips containing all zeros (0000) until valid data is again available within the FIFO. Once data resides within the bottom entry of the transmit FIFO, a new data frame is initiated by transmitting 16 preambles and a start flag followed by the transmission of data from the FIFO. When the TUR bit is set, an interrupt request is made unless it is masked. When TUS=0, the interrupt is masked; when TUS=1, it is enabled. Note that underruns are not generated when the HSSP transmitter is first enabled and is in the idle state (continuously transmits flags).

11.10.10.3 Receiver Abort Status (RAB) (read/write, nonmaskable interrupt)

The receiver abort status bit (RAB) is set when an abort is detected during receipt of an incoming frame. An abort is signalled when two or more chips that do not contain any pulses (0000) or chips containing 0011, 1001, 1010, or 0101(invalid chips not contained within the stop flag) are detected after a valid start flag has been detected but before a complete stop flag has been received (an incorrect chip in the stop flag generates an abort as well). When an abort is received, the EOF tag is set in the FIFO entry that corresponds to the last piece of data received before the frame was aborted. The receiver then enters hunt mode, searching for the preamble.

SA-1100 Developer’s Manual 11-121