Intel SA-1100 manual Software Dcache Flush, Dcaches Enable/Disable and Reset, Doubly Mapped Space

Caches, Write Buffer, and Read Buffer

6.2.3Software Dcache Flush

The SA-1100 supports the flush and clean operations on single entries of the Dcaches by writes to the cache operations registers. The flush whole cache is also supported. Note that since this is a write-back cache, in order to prevent the loss of data, a flush whole must be preceded by a sequence of loads to cause the cache to write back any dirty entries. The memory controller in the SA-1100 provides an internally decoded memory space to perform coherent Dcache flushing. This space resides in the upper 512 megabytes of the memory map (starting at virtual address 0hE000 0000) and, when accessed, is detected by the memory controller, which then returns zeros without incurring an external memory latency.

The following code causes the main data cache to flush all dirty entries:

;+ ;Call:

;R0 points to the start of a 8192 byte region of readable data used

;only for this cache flushing routine.

;bl writeBackDC

;Return:

;R0, R1, R2 trashed

;Data cache is clean

;-

writeBackDC movr0, 0hE0000000 addr1, r0, #8192

l1

ldr r2, <r0>, #32 teqr1, r0 bnel1

mcrp15, 0, r0, c7, c6, 0 movpc, r14

A similar routine may be written to flush the minicache. To perform this flush, the MMU B and C settings must be as described above. The invalidate-all operation also invalidates the minicache.

6.2.3.1Doubly Mapped Space

Since the Dcaches work with virtual addresses, it is assumed that every virtual address maps to a different physical address. If the same physical location is accessed by more than one virtual address, the cache cannot maintain consistency, since each virtual address has a separate entry in the cache, and only one entry is updated on a processor write operation. To avoid any cache inconsistencies, doubly mapped virtual addresses should be marked as noncacheable.

6.2.4Dcaches Enable/Disable and Reset

The Dcaches are automatically disabled and flushed on the assertion of nRESET. Once enabled, cacheable read accesses cause lines to be placed in the Dcaches. If subsequently disabled, no new lines are placed in the Dcaches, but they are still searched and if the data is found, it is used by the processor. Write operations continue to update the Dcaches, thus maintaining consistency with the external memory. If the data in the Dcaches must not be used, then the Dcaches must be flushed.

6-4 SA-1100 Developer’s Manual