Intel SA-1100 9.6 Reset Controller

SA-1100 Developer’s Manual 9-41
System Control Module
9.6 Reset Controller
The reset controller manages the various reset sources within the SA-1100. From a programmer’s
view, it is visible as two registers: one used to invoke software reset and one to read status after
booting to indicate why the processor was reset.
The four types of reset in the SA-1100 include:
•Hardware rese t
Hardware reset is invoked when the nRESET pin is asserted and resets all units in the SA-1100
to a known state. Hardware reset is intended to be used for power-up only. Because the
memory controller receives a full reset, all DRAM contents will be lost during hardware reset.
The RESET_OUT pin is asserted during hardware reset.
•Software reset
Software reset is invoked when the software reset (SWR) bit in the RSRR is set by software.
Software reset applies reset to the majority of the SA-1100 as well as causing the assertion of
the RESET_OUT pin. During software reset, the DRAM refresh and configuration are not
cleared. This allows DRAM contents to survive a software reset. After the SWR bit is set, the
SA-1100 stays reset for 256 processor clocks and then is allowed to boot again.
•Watchdo g reset
Watchdog reset is invoked when the watchdog enable bit (WE) in the OWER is set and the
OSMR3 matches the OS timer counter. When watchdog reset is invoked, the rest of the reset
sequence is identical to software reset. The watchdog enable bit cannot be cleared under
program control. Only one of the four reset types can clear it.
•Sleep reset
Sleep reset is invoked automatically when the SA-1100 enters sleep mode. During sleep mode,
the majority of the processor loses power and will receive reset prior to the negation of the
PWR_EN pin. Sleep reset does not affect the power manager, R TC, or GPIO wake-u p register.
During sleep reset, although the memory controller is in reset, the RAS<3:0> and CAS<3:0>
pins are held in the self-refresh state required by the DRAMs.
After booting from a reset, software can examine the reset controller reset status register (RCSR)
to determine which types of reset caused the reset condition.