Intel SA-1100 PPC Pin Assignment Register, Uart Pin Reassignment UPR, SSP Pin Reassignment SPR

Peripheral Control Module

11.13.5PPC Pin Assignment Register

The UART in serial port 1 and the SSP in serial port 4 can be reassigned to GPIO pins using the PPC pin assignment register (PPAR). The PPAR contains two bits that control the reassignment of each serial engine to an individual set of GPIO pins.

11.13.5.1UART Pin Reassignment (UPR)

The UART pin reassignment (UPR) bit is used to select whether serial port 1’s UART is assigned to GPIO pins 14 and 15. When UPR=0, serial port 1 uses its TXD1 and RXD1 pins, and the SDLC/UART select (SUS) bit is used to select which protocol is enabled. When UPR=1, SUS is ignored, serial port 1 defaults to SDLC operation using the TXD1 and RXD1 pins, and the UART is configured to use GPIO<14> for transmit and GPIO<15> for receive. Note that the user must set bits 14 and 15 in the GPIO alternate function register (GAFR) as well as set bit 14 and clear bit 15 in the GPIO pin direction register (GPDR). See the Section 9.1, “General-Purpose I/O” on

page 9-1.

11.13.5.2SSP Pin Reassignment (SPR)

The SSP pin reassignment (SPR) bit is used to select whether serial port 4’s SSP is assigned to GPIO pins 10 through 13. When SPR=0, serial port 4 uses its TXD4, RXD4, SCLK, and SFRM pins; the MCP enable (MCE) and SSP enable (SSE) bits are used to select which protocol is enabled (MCE has precedence over SSE). When SPR=1, MCE and SSE must both be set; serial port 4 defaults to MCP operation using the TXD4, RXD4, SCLK, and SFRM pins, and the SSP is configured to use GPIO<10> for transmit, GPIO<11> for receive, GPIO<12> for serial clock, and GPIO<13> for serial frame. Note that the user must set bits 10 through 13 in the GPIO alternate function register (GAFR) as well as set bits 10, 12, and 13 and clear bit 11 in the GPIO pin direction register (GPDR). See the Section 9.1, “General-Purpose I/O” on page 9-1 .

The following table shows the location of the two pin reassignment bits. Note that for reserved bits, writes are ignored and reads return zero. Both control bits are cleared to zero following a reset of the SA-1100, giving control of all GPIO pins to the system control module.

Address: 0h 9006 0008						PPAR: PPC Pin Assignment Register								Read/Write
Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							Reserved							SPR	Reserved
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		Reserved		UPR						Reserved
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Bit	Name	Description
11..0	—	Reserved.
12	UPR	UART pin reassignment.
		0 – No pin reassignment made, GPIO<14-15> controlled by GPIO unit, serial port 1
		UART assigned to TXD1 and RXD1 if SUS=1.
		1 – Pin reassignment made, serial port 1 defaults to SDLC operation (SUS ignored),
		UART transmit assigned to GPIO<14> and receive to GPIO<15>, GAFR and GPDR
		must be configured in GPIO unit.
17..13	—	Reserved.
18	SPR	SSP pin reassignment.
		0 – No pin reassignment made, GPIO<10-13> controlled by GPIO unit, serial port 4
		SSP assigned to TXD4, RXD4, SCLK, and SFRM if MCE=0 and SSE=1.
		1– Pin reassignment made, serial port 4 defaults to MCP operation, SSP transmit
		assigned to GPIO<10>, receive to GPIO<11>, serial clock to GPIO<12>, and serial
		frame to GPIO<13>, GAFR and GPDR must be configured in GPIO unit.
31..19	—	Reserved.

SA-1100 Developer’s Manual 11-189