Intel SA-1100 manual High-Speed ICP Operation, 11.10.2.1 4PPM Modulation, Chip Timeslots Data =

Peripheral Control Module

Figure 11-25. UART Frame Format for IrDA Transmission (<= 115.2 Kbps)

Start Bit Data<7> Data<6>

Data<5>

Data<4> Data<3>

Data<2>

Data<1>

Data<0> Stop Bit

UTCR0-2 Programming:
PE=0	DSS = 1	TCE = don’t care	RXE = 1	RIE = 0 or 1
OES = don’t care	SCE = 0	BRD = 0x001 to	TXE = 1	TIE = 0 or 1
SBS = 0	RCE = don’t care	0xFFF	BRK = 0

11.10.2High-Speed ICP Operation

Before enabling the ICP for high-speed operation, the user must first clear any writable or “sticky” status bits that are set by writing a one to each bit. Next, the desired mode of operation is programmed in the control registers. At this point the user can “prime” the HSSP’s transmit FIFO by writing up to 16 values, or the FIFO can remain empty and either programmed I/O or the DMA can be used to service it after the HSSP is enabled. Once the HSSP is enabled, transmission/reception of data can begin on the transmit (TXD2) and receive (RXD2) pins.

For high-speed operation, all serial data, which is transferred between the TXD2/RXD2 pins and the ICP’s HSSP, is modulated/demodulated according to the 4PPM IrDA standard. Additionally, the HSSP uses a frame format that is very similar to the SDLC’s. For high-speed transmission, both the modulation technique and the HSSP’s frame format are discussed in the following sections.

11.10.2.14PPM Modulation

Four-position pulse modulation (4PPM) is used for the high-speed transmission rate of 4.0 Mbps. Two data bits are encoded at a time by placing a single 125 ns light pulse within one of four timeslots. The four timeslots are collectively termed a “chip.” Bytes are encoded one at a time. They are divided into four individual nibbles (2-bit pairings) and the least significant nibble is transmitted first. Figure 11-26shows the 4PPM encoding for the four possible 2-bit combinations and Figure 11-27shows an example of 4PPM modulation of the byte 8’b10110001 that is constructed using four chips. Note that bits within each nibble are not reordered, but nibble 0 (least significant) is transmitted first, ending with nibble 3 (most significant).

Figure 11-26. 4PPM Modulation Encodings

1

Chip

Timeslots

2 3

4

Data = 00

Data = 01

Data = 10

Data = 11

SA-1100 Developer’s Manual 11-105