RDNx40 ROM delay next access | Intel SA-1100 manual

		Memory and PCMCIA Control Module

Bit	Name	Description

12..8	RDNx<4:0>	ROM delay next access.
		Number of memory clock cycles (minus 1) from address to data valid for subsequent
		accesses of a burst ROM.
		For Flash and SRAM, this determines the write pulse width.
		One memory clock cycle is added to this value.

15..13	RRRx<2:0>	ROM/SRAM recovery time.
		Number of memory clock cycles (divided by 2) from chip select deasserted after a
		read to next chip select (of a different memory bank) or nRAS asserted. nCS
		negated to nRAS asserted is 2*RRR or 1 cycle (whichever is greater).
		For Flash and SRAM, this field will also be used after writes to hold off subsequent
		accesses.
		This field should be programmed with the maximum of Toff, write pulse high time
		(Flash/SRAM), and write recovery before read (Flash).

1When SMCNFGx:RT=01, accesses to the selected bank will output a byte mask on nCAS<3:0> for both reads and writes. This option should be selected only when there is no DRAM in the system.

SA-1100 Developer’s Manual

10-11

Page 125

Image 125

Intel SA-1100 manual RDNx40 ROM delay next access, Accesses of a burst ROM

Contents

Developer’s Manual Intel StrongARM SA-1100 Microprocessor SA-1100 Developer’s Manual Contents Memory-Management Unit MMU Caches, Write Buffer, and Read Buffer System Control Module 1.6 Memory and Pcmcia Control Module Reviving the DRAMs from Self-Refresh Mode Peripheral Control Module 11-39 11.8.3.4Endpoint 0 Interrupt Mask EIM 11-64 11.8.3.5Receive 11-81 SA-1100 Developer’s Manual 11-128 Serial Port 4 MCP / SSP 11-169 11.12.12.1Transmit Fifo Not Full Flag TNF Internal Test Register Summary MHz Oscillator SpecificationsKHz Oscillator Specifications Figures Tables SA-1100 Power and Clock Supply Sources and States 14-4 Page Intel StrongARM SA-1100 Microprocessor IntroductionLCD DMA Features of the SA-1100 CPU for CA and DA Parts Features of the SA-1100 CPU for AA and EA Parts Changes to the SA-1100 Core from the SA-110 Additional Features Built into SA-1100 Chipset Overview SA-1100 Example System Example System ARM Architecture Read Buffer Write BufferPage Functional Description Block Diagram SA-1100 Block Diagram Inputs/Outputs Name Type Description Signal DescriptionSignal Descriptions Sheet 1 Signal Descriptions Sheet 2 TDO OCZ Signal Descriptions Sheet 3VDD VSS Memory Map Pcmcia Interface Mbyte Static Memory ROM, Flash, Sram 1GB Exceptions ARM Implementation OptionsBig and Little Endian ROM Size Select Power-Up Reset Abort Vector Summary Address Exception Mode on EntryException Priorities Vector Summary Coprocessors Interrupt Latencies and Enable TimingPage Instruction Set Instruction Group Result Delay Issue CyclesInstruction Set Instruction TimingsPage Internal Coprocessor Instructions Coprocessors Register 0 ID Coprocessor 15 DefinitionCache and MMU Control Registers Coprocessor Register Register Reads Register Writes Register 1 Control Register 5 Fault Status Register 3 Domain Access ControlRegister 6 Fault Address Register 2 Translation Table Base Register 8 TLB Operations Register 7 Cache Control OperationsFunction OPC2 Registers 10 12 Reserved Register 9 Read-Buffer Operations CRm Access process ID register 0b000 0b0000Register 13 Process ID Virtual Address Mapping Dbcr Bit Action Register 14 Debug Support Breakpoints 0b010 0b0100 Wait for interrupt 0b1000 Register 15 Test, Clock, and Idle ControlPage Instruction Cache Icache Caches, Write Buffer, and Read BufferIcache Operation Icache Validity Data Caches Dcaches Icache Enable/Disable and ResetEnabling the Icache Disabling the Icache Bufferable Bit B Cacheable Bit CCacheable Reads C = Noncacheable Reads C = Doubly Mapped Space Dcaches Enable/Disable and ResetSoftware Dcache Flush Write Buffer Operation Write Buffer WBBufferable Bit Enabling the Write Buffer Read Buffer RBWrites to a Bufferable and Noncacheable Location B=1,C=0 Unbufferable Writes B=0 Caches, Write Buffer, and Read Buffer Page Memory-Management Unit MMU MMU Faults and CPU AbortsData Aborts MMU Registers Cacheable Reads Linefetches Interaction of the MMU, Icache, Dcache, and Write BufferBuffered Writes Valid MMU, Dcache, and Write Buffer Combinations Mini Data Cache To disable the MMUPage SA-1100 Crystal Oscillators ClocksRTC ARM Restrictions on Changing the Core Clock Configuration Core Clock Configuration RegisterCore Clock Configurations CCF40 Core Clock Frequency in MHz MHz Crystal Oscillator Driving SA-1100 Crystal Pins from an External Source Clocking During Test General-Purpose I/O System Control Module Gpio Pin Edge Detect Gpio Register Definitions Bit Name Description Gpio Pin-Level Register Gplr Gpio Pin Direction Register Gpdr Bit Reset PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 31..28 Reserved Bit Name Description Gpio Rising-Edge Detect Register GrerBit Name Description Gpio Falling-Edge Detect Register Grer Gpio Edge Detect Status Register Gedr Gpio Alternate Function Register Gafr Gpio Alternate Functions Pin Alternate Function Direction Unit Signal Description Address Name Description Gpio Register Locations Interrupt Controller Register Definitions Interrupt ControllerInterrupt Bits Interrupt Bit Field Description Interrupt Controller Pending Register IcprBit Position Unit Source Module IP9 IP8 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 Interrupt Controller Mask Register Icmr IMn Interrupt mask n where n = 0 through Bit Name Interrupt Controller Level Register Iclr Idle mode. This bit is cleared during all resets Disable idle maskInterrupt Controller Control Register Iccr DIM RTC Counter Register Rcnr Real-Time ClockInterrupt Controller Register Locations RTC Status Register Rtsr RTC Alarm Register RtarALE HZE Oscillator Frequency Calibration Trim ProcedureRTC Trim Register Rttr Trim Example #1 Measured Value Has No Fractional Component Rttr Value Calculations Real-Time Clock Register Locations Operating System Timer OS Timer Match Registers 0-3 OSMR0, OSMR1, OSMR2, OSMR3 OS Timer Count Register OscrOS Timer Watchdog Match Enable Register Ower WME OS Timer Status Register Ossr Interrupt enable channel OS Timer Interrupt Enable Register OierWatchdog Timer OS Timer Register Locations OS Timer Register Locations Run Mode Power ManagerIdle Mode Entering Idle Mode Exiting Idle Mode Sleep ModeCPU Preparation for Sleep Mode Events Causing Entry into Sleep Mode Sleep Wake-Up Sequence During Sleep ModeSleep Shutdown Sequence Booting After Sleep Mode Reviving the DRAMs from Self-Refresh Mode Assumed Behavior of an SA-1100 System in Sleep Mode Idle Sleep Hardware ResetRUN Pin Name Type Pin Operation in Sleep ModePin State During Step Power Manager Control Register Pmcr Power Manager Registers Opde Power Manager General Configuration Register Pcfr Power Manager PLL Configuration Register Ppcr WEn Power Manager Wake-Up Enable Register Pwer VFS Power Manager Sleep Status Register PssrBFS Dram control hold Bit is cleared. This bit is cleared on hardware resetPeripheral control hold 31..5 Reserved Power Manager Gpio Sleep State Register Pgsr Power Manager Scratch Pad Register Pspr Power Manager Register Locations Power Manager Register LocationsPower Manager Oscillator Status Register Posr Hardware reset Reset Controller Reset Controller Software Reset Register Rsrr Reset Controller RegistersSoftware reset SWR Reset Controller Register Locations Reset Controller Register LocationsReset Controller Status Register Rcsr Page Overview of Operation Memory and Pcmcia Control ModuleIntel SA-1100 Memory Controller Interface 10-2 Memory and Pcmcia Control Module Example Memory System Example Memory Configuration Reads Types of Memory AccessesWrites Transaction Summary Aborts and Nonexistent Memory Read-Lock-WriteSA-1100 Transactions Bus Operation Memory Interface Control Registers Memory Configuration RegistersPhysical Address Symbol Register Name CDB2 Dram Configuration Register Mdcnfg Cycle 31..17 DRI140 Dram refresh intervalMem clock frequency /4 Will not be interrupted Dram CAS Waveform Shift Registers MDCAS0, MDCAS1, MDCAS2 For Flash and SRAM, this determines the read access time ROM or the first access of a burst ROMStatic Memory Control Registers MSC1-0 One memory clock cycle is added to this value For Flash and SRAM, this determines the write pulse width 12..8 RDNx40 ROM delay next accessAccesses of a burst ROM Expansion Memory Pcmcia Configuration Register Mecr Bclk Speeds for 160-MHz Processor Core Frequency BSxx Bit EncodingBclksel Bclk Cycle Time-ns Dram Overview Dynamic Interface OperationDram Memory Size Options Dram Row/Column Address Multiplexing Dram Timing Mdcnfgtrp = 4 MDCNFGCDB2 = Addr Dram Burst-of-Eight Transactions Static Memory Interface Dram Self-Refresh in Sleep ModeDram Refresh 10-18 ROM Interface Overview ROM Timing Diagrams and Parameters A42 A255Input Data Latch 10-20 SA-1100 Developer’s Manual Eight Beat Burst Read from Burst-of-Four ROM Sram Interface Overview Sram Timing Diagrams and ParametersSram Write Timing Diagram 4-Beat Burst Flash Eprom Interface Overview 10-24 Flash Eprom Timing Diagrams and Parameters Dram Access Followed by a Static Access Static Access Followed by a Dram AccessDram Access Followed by a Refresh Operation General Memory BUS Timing 10-26 Pcmcia Overview Address 10.6.1 32-Bit Data Bus Operation 10-28 External Logic for Pcmcia Implementation 12. Pcmcia External Logic for a Two-Socket Configuration 10-30 13. Pcmcia External Logic for a One-Socket Configuration 14. Pcmcia Voltage-Control Logic Pcmcia Interface Timing Diagrams and Parameters 10-32 15. Pcmcia Memory or I/O 16-Bit Access 16. Pcmcia I/O 16-Bit Access to 8-Bit Device 10-34 Flow of Events After Reset or Exiting Sleep ModeInitialization of the Memory Interface Alternate Memory Bus Master Mode Page Read/Write Interface Peripheral Control Module Peripheral Register Width DMA Burst Size Memory Organization Peripheral Serial Protocol Base Address Peripheral Units’ Base AddressesLCD Controller 0h B010 Serial Port ICP Hssp Peripheral Units’ Interrupt Numbers InterruptsInterrupt Peripheral Peripheral Gpio Pin Function Peripheral PinsDedicated Peripheral Pins Peripheral Unit Gpio Pin Assignment Use of the Gpio Pins for Alternate Functions DMA Register Definitions DMA Controller DMA Device Address Register DDARn Device From To Half-word wide To From Byte-wide D31 D0 1 0 from memoryController From Half-word wide 11-10 Valid Settings for the DDARn RegisterDdar Fields Unit Name Function Address DA318 DS30 DMA Control/Status Register DCSRn DMA Buffer a Transfer Count Register DBTAn DMA Buffer a Start Address Register DBSAn DMA Buffer B Start Address Register DBSBn DMA OperationDMA Buffer B Transfer Count Register DBTBn TCB120 Transfer count buffer B DMA Register List Physical Address Register Name Symbol DBTA3 DBSA3DBSB3 DBTB3 11-16 LCD Controller Lpclk DMA to Memory Interface LCD Controller OperationFrame Buffer 11-18 PBS Pixel bit size 13..12To palette Frame to palette Encoded Pixel Data150 Encoded Pixel Data70 BitUnused Red Data30 Green Data30 Blue Data30 11-22 FrameBufferSize = 32 + 16 + è Lookup Palette Input Fifo Output Fifo Color/Gray-Scale DitheringColor/Gray-Scale Intensities and Modulation Rates Dither Value Intensity Modulation Rate LCD Controller Register Definitions LCD Controller Pins LCD Controller Control Register LCD Enable LENColor/Monochrome Select CMS Single-/Dual-Panel Select SDS Dual Panel Active Panel Single Passive Screen Portion PinsLCD Controller Data Pin Utilization 11-28 LCD Data-Pin Pixel Ordering Base Address Update Interrupt Mask BAM LCD Disable Done Interrupt Mask LDMError Interrupt Mask ERM Passive/Active Display Select PAS 11-30 11.7.3.8 Big/Little Endian Select BLE Double-Pixel Data DPD Pin ModePalette DMA Request Delay PDD CMS LENSDS LDM BLE PASDPD PDD Horizontal Sync Pulse Width HSW Pixels Per Line PPLEnd-of-Line Pixel Clock Wait Count ELW 11-34 PPL Beginning-of-Line Pixel Clock Wait Count BLWHSW ELW 11-36 Lines Per Panel LPPVertical Sync Pulse Width VSW Beginning-of-Frame Line Clock Wait Count BFW End-of-Frame Line Clock Wait Count EFW VSW LPPEFW BFW AC Bias Pin Frequency ACB Pixel Clock Divider PCD Vertical Sync Polarity VSP AC Bias Pin Transitions Per Interrupt APIHorizontal Sync Polarity HSP Pixel Clock Polarity PCP Address 0h B010 Output Enable Polarity OEP HSP LCD Controller DMA RegistersPCP OEP 31..0 DMA Channel 1 Base Address RegisterDBAR1 DMA channel 1 base address pointer DCAR1 DMA Channel 1 Current Address RegisterDMA channel 1 current address pointer Equal to the calculated end address of the buffer DBAR2 DMA Channel 2 Base and Current Address RegistersDCAR2 DMA channel 2 current address pointer Base Address Update Flag BAU read-only, maskable interrupt LCD Disable Done Flag LDD read/write, maskable interruptBus Error Status BER read/write, maskable interrupt LCD Controller Status Register AC Bias Count Status ABC read/write, nonmaskable interrupt BAU LDD ABC BERIOL IUL LCD Controller Control, DMA, and Status Register Locations LCD Controller Register Locations LDDx0 LCD Controller Pin Timing Diagrams 11-52 Lfclk Llclk LpclkLDDx0 DPD = 12. Passive Mode Pixel Clock and Data Pin Timing 11-54 13. Active Mode Timing 14. Active Mode Pixel Clock and Data Pin Timing 11-56 Serial Port 0 USB Device ControllerUSB Operation 10. USB Bus States Signalling LevelsBus State UDC+/UDC- Pin Levels Port 11-58 Bit EncodingBit Value Digital Data Nrzi Data 11. Endpoint Field Addressing Field FormatsEndpoint Field Value UDC Endpoint Selected Endpoint PID Packet FormatsCRC5 CRC16 Action Transaction FormatsOUT Packets from UDC to host are boldface UDC Device Requests Setup DATA0Action Token Packet Data Packet 11-62 Request Name UDC Register Definitions12. Host Device Request Summary UDC Control Register Suspend/Resume Interrupt Mask SRM Reset Interrupt Mask REMAddress 0h 8000 Udccr UDC OUT Max Packet Register UDC Address RegisterUdcar Udcomp Udcimp UDC in Max Packet RegisterAddress 0h 8000 000C UDC Endpoint 0 Control/Status Register UDCCS0 Serviced Setup End SSESSE FST SST IPR OPR SSE Receive Packet Error RPE Receive Fifo Service RFSUDC Endpoint 1 Control/Status Register Receive Packet Complete RPC UDCCS1 Bits 7..6 ReservedRNE FST SST RPE RPC RFS RNE Transmit Packet Error TPE Transmit Fifo Service TFSUDC Endpoint 2 Control/Status Register Transmit Packet Complete TPC FST SST TUR TPE TPC TFS UDCCS2 UDC Endpoint 0 Write Count Register UDC Endpoint 0 Data RegisterUDCD0 Data Uddr UDC Data RegisterTop/bottom of transmit/receive Fifo data Read Bottom of receive Fifo data UDC Status/Interrupt Register Udcsr Reset Interrupt Request RstirRstir Resir Susir TIR RIR EIR Rstir 13. UDC Control, Data, and Status Register Locations Serial Port 1 SDLC/UARTUDC Register Locations Sdlc Operation Address Field Frame FormatControl Field CRC-CCITT Baud Rate Generation Data FieldCRC Field 11-82 Receive Operation Simultaneous Use of the Uart and Sdlc Transmit Operation Sdlc Register Definitions CPU and DMA Register Access SizesTransmit and Receive FIFOs 11-84 Sdlc Control Register Loopback Mode LBMSDLC/UART Select SUS Single/Double Flag Select SDF Bit Modulation Select BMS Sample Clock Enable SCESample Clock Direction SCD 11-86 Transmit Clock Edge Select TCE Receive Clock Edge Select RCEAddress 0h 8002 SDCR0 TCE Abort After Frame AAF Receive Enable RXE Transmit Enable TXEReceive Fifo Interrupt Enable RIE Transmit Fifo Interrupt Enable TIE Receiver Abort Interrupt EnableRAE Address Match Enable AMETransmit Fifo Underrun Select TUS 11-90 Read/Write SDCR1RAE TUS AME TIE RIE RXE TXE AAF RAE AMV Address Match Value AMVSDCR2 Baud Rate Divisor BRD Sdlc Control Registers 3Address 0h 8002 006C SDCR3 11-94 Sdlc Data Register Sddr Address 0h 0078ROR CRE EOF ROR Transmit Underrun Status TUR read/write, maskable interrupt Sdlc Status RegisterReceiver Abort Status RAB read/write, maskable interrupt 11-96 SA-1100 Developer’s Manual 11-97 RFS TFS RAB TUR EIF SDSR0 Transmitter Busy Flag TBY read-only, noninterruptible Receiver Synchronized Flag RSY read-only, noninterruptibleReceive Fifo Not Empty Flag RNE read-only, noninterruptible Transmit Fifo Not Full Flag TNF read-only, noninterruptible 11-100 CRC Error Status CRE read-only, noninterruptibleReceiver Overrun Status ROR read-only, noninterruptible ROR CRE EOF RTD TNF RNE SDSR1RSY TBY 14. Uart Control, Data, and Status Register Locations Uart Register Locations 15. Sdlc Control, Data, and Status Register Locations Serial Port 2 Infrared Communications Port ICPSdlc Register Locations HP-SIR*Modulation Low-Speed ICP OperationUart Frame Format 11-104 Chip Timeslots Data = High-Speed ICP Operation11.10.2.1 4PPM Modulation Hssp Frame Format SA-1100 Developer’s Manual 11-107 11-108 SA-1100 Developer’s Manual 11-109 11-110 Low-Power Mode LPM HP-SIR Enable HSEUart Register Definition Uart Control Register Hssp Control Register Hssp Register DefinitionsIrDA Transmission Rate ITR LPM SA-1100 Developer’s Manual 11-113 11-114 AME TIM RIM RXE TXE TUS LBM ITR Address 0h 8004HSCR0 11-116 HSCR1Search for the next preamble Receive Pin Polarity Select RXP Transmit Pin Polarity Select TXP HSCR2 0h 9006RXP TXP RXP Hssp Data Register Hsdr Address 0h 8004 006CLast Fifo entry is transferred to the ROR bit HSSR1 Receiver Abort Status RAB read/write, nonmaskable interrupt Hssp Status Register 11-122 HSSR0 Framing Error Status FRE read/write, nonmaskable interruptFRE RFS TFS RAB TUR EIF FRE 11-124 End-of-Frame Flag EOF read-only, noninterruptible SA-1100 Developer’s Manual 11-125 ROR CRE EOF TNF RNE TBY RSY HSSR1 17. Hssp Control, Data, and Status Register Locations Hssp Register Locations16. Uart Control, Data, and Status Register Locations Uart Operation Serial Port 3 UartLSB MSB 11-128 30. NRZ Bit Encoding Example 0100 11-130 11.11.3.2 Odd/Even Parity Select OES Parity Enable PEUart Register Definitions 11-132 Stop Bit Select SBSData Size Select DSS TCE RCE SCE DSS SBS OES UTCR0 Uart Control Registers 1 Bit Reset BRD70UTCR1 UTCR2 Break BRK Receiver Enable RXETransmitter Enable TXE LBM TIE RIE BRK TXE RXE UTCR3 Uart Data Register ROR FRE PRE Utdr Uart Status Register 11-140 Error in Fifo Flag EIF read-only, nonmaskable interruptReceiver Idle Status RID read/write, maskable interrupt EIF REB RBB RID RFS TFS Address 0h 8005 001CUTSR0 11-142 Parity Error Flag PRE read-only, noninterruptible Receiver Overrun Flag ROR read-only, noninterruptible Framing Error Flag FRE read-only, noninterruptible ROR FRE PRE TNF RNE TBY UTSR1Read-Only Serial Port 4 MCP / SSP 11-146 MCP Operation 31. MCP Frame Data Format 11-148 Audio and Telecom Sample Rates and Data Transfer MCP Transmit and Receive Fifo Operation 11-150 Codec Control Register Data TransferBit Audio Data Telecom Data Alternate SSP Pin Assignment External Clock Operation MCP Control Register MCP Register DefinitionsAudio Sample Rate Divisor ASD 11-152 Telecom Sample Rate Divisor TSD 11.12.3.5 A/D Sampling Mode ADM Multimedia Communications Port Enable MCEExternal Clock Select ECS 11-154 Telecom Receive Fifo Interrupt Enable TRE Telecom Transmit Fifo Interrupt Enable TTEAudio Transmit Fifo Interrupt Enable ATE Audio Receive Fifo Interrupt Enable are ASD External Clock Prescaler ECPAudio sample rate divisor TSD ECS MCEADM TTE CFS MCP Data RegistersClock Frequency Select CFS Address 0h 8006 MCP Data Register 0 MCDR0 Read/Write MCP Data RegisterReserved for future enhancements 15..4 Address 0h 8006 000C MCP Data Register 1 MCDR1 Read/Write SA-1100 Developer’s Manual 11-161 Address 0h 8006 MCP Data Register 2 MCDR2 Read/Write Reg Address R/W Reset Bit15..0 Codec Register read Read/write Read Returns a zero MCP Status Register 11-164 SA-1100 Developer’s Manual 11-165 Telecom Codec Enabled Flag TCE read-only, noninterruptible Audio Codec Enabled Flag ACE read-only, noninterruptibleCodec Write Completed Flag CWC read-only, noninterruptible Codec Read Completed Flag CRC read-only, noninterruptible ARS ATSTTS TRS TRO TTUANF ANE SSP Operation 11-170 35. Texas Instruments* Synchronous Serial Frame Format 36. Motorola* SPI Frame Format 11-172 37. National Microwire* Frame Format Bit Bit Data SSP Transmit and Receive FIFOs 11-174 SSP Register DefinitionsSSP Control Register Frame Format FRF Synchronous Serial Port Enable SSE SCR Serial Clock Rate SCRFRF Serial Clock Polarity SPO Sclk SPO=0 Sclk SPO=1 Sfrm TXD4 RXD4 Serial Clock Phase SPHLSB 11-178 SPO Justifies data and zero fills unused bits 11-180 SSP Data RegisterAddress 0h 8007 006C SSP Busy Flag BSY read-only, noninterruptible SSP Status Register BSY SSP Register Locations MCP Register Locations19. MCP Control, Data, and Status Register Locations 20. SSP Control, Data, and Status Register Locations 11-184 Peripheral Pin Controller PPCPPC Operation PPC Pin Direction Register PPC Register Definitions Sclk Address 0h 9006 Ppsr PPC Pin StateRegister Read/Write PPC Pin State Register Read Current state of LCD pixel clock pin returned LCD pixel clock pin stateLCD line clock pin state Read Current state of LCD line clock pin returned Uart Pin Reassignment UPR PPC Pin Assignment RegisterSSP Pin Reassignment SPR UPR 11-190 PPC Sleep Mode Pin Direction Register LCD pixel clock pin configured as input during sleep LCD pixel clock sleep mode pin directionLCD line clock sleep mode pin direction LCD line clock pin configured as input during sleep PPC Pin Flag Register 21. PPC Control and Flag Register Locations PPC Register LocationsPage DC Parameters Symbol Parameter Min Max UnitsAbsolute Maximum Ratings SA-1100 DC Maximum Ratings DC Operating Conditions Symbol Parameter Min Nom Max UnitsSA-1100 DC Operating Conditions × Vddx Parameter SA-1100 Units Power Supply Voltages and CurrentsVDD VddxPage SA-1100 Output Derating AC ParametersTest Conditions Module Considerations Memory Bus and Pcmcia Signal TimingsMemory Bus Memory Bus Out 13-2 LLDD70 fall LCD Controller SignalsMCP Signals Timing Parameters Pin Name Symbol Parameter Min Max UnitSA-1100 AC Timing Table for AA and BA Parts Sfrmc Asynchronous Signal Timing Descriptions Page Mechanical Data and Packaging Information Package and Pinout 14-2 SA-1100 Pinout 208-Pin Quad Flat Pack SA-1100 256 Mini-Ball Grid Array Mechanical Drawing Mini-Ball Grid Array mBGA 14-4 SA-1100 Pinout 256-Pin Mini-Ball Grid Array Data Breakpoint Debug SupportInstruction Breakpoint Page Boundary-Scan Test Interface Test Access Port TAP Controller State Transitions Pull-Up Resistors ResetInstruction Register Public Instructions Clamp ExtestSAMPLE/PRELOAD Idcode HighzBypass 16-4 Bypass Register Test Data Registers 16-6 16.6.2 SA-1100 Device Identification ID Code Register16.6.3 SA-1100 Boundary-Scan BS Register Tbscl Tbsch Boundary-Scan Interface SignalsTbsis Tbsih Tbsoh Tbsod Data Tbsss Tbssh Data Out Tbsdh Tbsdd Data Out Tbsde TbsoeTbsr Tbsrs Tbsrh SA-1100 Boundary-Scan Interface Timing Symbol Parameter Minimum Typical Maximum UnitsPage Register Summary Tucr DMA control/status register 2 write ones to set B000 0044B000 0048 Write ones to clear 004C Read only 0050 B000 0054 Ucdomp 8031 Sdlc Registers Serial Port 80028003 Reserved 8003 001C 8004 007C 0h 8004 Ffff Reserved 9006 0034 0h 9006 Ffff Reserved Uart Registers Serial Port 80058007 0078 0h 8007 Ffff Reserved PPC Registers 9006 System Specifications MHz Oscillator Specifications BSpecifications Specification Minimum Typical Maximum Unit MHz Oscillator Specifications Typical Maximum Unit Quartz Crystal SpecificationSpecification Page Temperature Range KHz Oscillator Specifications CCurrent Consumption Startup Time Parasitic Capacitance Off-chip Between Txtal and Textal Frequency Shift Due to Temperature Effect on the CircuitParasitic Resistance Between Txtal and Textal Parasitic Resistance Between Txtal or Textal and VSS Therefore, the values for Q Other providers supply a Quality Factor, Q, instead of RmCorresponding to specified range of Rm are supplied Following table KHz Oscillator Specifications PMD Internal TestTest Unit Control Register Tucr TSEL2 TSEL1 TSEL0 TSEL2-0Page Support, Products, and Documentation

Memory and PCMCIA Control Module

Bit

12..8

RDNx<4:0>

ROM delay next access.

accesses of a burst ROM.

For Flash and SRAM, this determines the write pulse width.

One memory clock cycle is added to this value.