Intel manual SA-1100 Block Diagram

Functional Description

Figure 2-1shows the functional blocks contained in the SA-1100 integrated processor. Figure 2-2is a functional diagram of the SA-1100.

Figure 2-1. SA-1100 Block Diagram

3.686 MHz

32.768 KHz

						Instruction				Intel®
										StrongARM® *
										SA-1100
OSC	PLL		IMMU			Icache	PC			JTAG
					(16 Kbytes)
								ARM™*		and
								SA-1		Misc
OSC						Dcache	Addr			Test
			DMMU					Core
						(8 Kbytes)
						Minicache
	RTC	Processing				Load/Store Data
OS Timer		Core
	General-
Purpose I/O						Write		Read
	Interrupt					Buffer		Buffer
Controller										Memory
	Power									and
		System								PCMCIA
Management				System Bus
	Reset	Control								Control
										Module
		Module
Controller										(MPCM)
			(SCM)				DMA		LCD
						Bridge
							Controller		Controller
	Peripheral Control
	Module (PCM)
	Peripheral Bus
	Serial			Serial		Serial		Serial		Serial
	Channel 0		Channel 1			Channel 2		Channel 3		Channel 4
	UjSB			SDLC		IrDA		UART		CODEC

* ARM is a trademark and StrongARM is a registered trademark of ARM Limited.

A6832-01

2-2 SA-1100 Developer’s Manual