Intel SA-1100 manual Bits 7..6 Reserved, UDCCS1, Rne Fst Sst Rpe Rpc Rfs

Peripheral Control Module

11.8.8.7Bits 7..6 Reserved

Bits 7..6 are reserved for future use.

	Address: 0h 8000 0014			UDCCS1			Read/Write
Bit	7	6	5	4	3	2	1		0
		Res.	RNE	FST	SST	RPE		RPC	RFS
Reset	0	0	0	0	0	0	0		0

Bit	Name		Description
		Receive FIFO service (read-only).
0	RFS	0 – Receive FIFO has less than 12 bytes.
		1	– Receive FIFO has 12 bytes or more.
		Receive packet complete (read/write 1 to clear).
1	RPC	0 – Error/status bits invalid.
		1	– Receive packet has been received and error/status bits are valid.
		Receive packet error (read-only).
2	RPE	0 – Receive packet has no errors.
		1	– Receive packet has errors; valid only when RPC is set.
3	SST	Sent stall (read/write 1 to clear).
		1	– STALL handshake was sent; valid only when RPC is set.
4	FST	Force stall (read/write).
		1	– Issue STALL handshakes to OUT tokens.
		Receive FIFO not empty (read-only).
5	RNE	0 – Receive FIFO empty.
		1	– Receive FIFO not empty.
7..6	—	Reserved.
		Always reads zero.

SA-1100 Developer’s Manual 11-71