Intel SA-1100 10.2 Memory Configuration Registers

10-6 SA-1100 Developer’s Manual
Memory and PCMCIA Control Module
10.2 Memory Configuration Registers
The SA-1100 memory interface is programmed through a set of configuration registers that are
described in the following sections.
Table10-2 shows the registers associated with the memory interface and the physical addresses
used to access them. All addressing is little endian. These registers are readable and writable only
as full words. They are grouped together within one page and thus all have the same memory
protections.
Table 10-2. Memory Interface Control Registers
Physical Address Symbol Register Name
0xA000 0000 MDCNFG DRAM configuration register
0xA000 0004 MDCAS0 DRAM CAS waveform shift register 0
0xA000 0008 MDCAS1 DRAM CAS waveform shift register 1
0xA000 000C MDCAS2 DRAM CAS waveform shift register 2
0xA000 0010 MSC0 Static memory control register 0
0xA000 0014 MSC1 Static memory control register 1
0xA000 0018 MECR Expansion bus configuration register