Intel manual SA-1100 Developer’s Manual 11-109

Peripheral Control Module

When the receive FIFO is one- to two-thirds full, an interrupt or DMA transfer is signalled. If the data is not removed soon enough and the FIFO is completely filled, an overrun error is signalled when the receive logic attempts to place additional data into the full FIFO. Once the FIFO is full, all subsequent data bytes received are lost while all FIFO contents remain intact.

If any two sequential chips within the data field do not contain pulses (are 0000), the frame is aborted, the least recent or oldest byte within the temporary FIFO is moved to the receive FIFO (the remaining four FIFO entries are discarded), the end-of-frame (EOF) tag is set within the same FIFO entry where the last “good” byte of data resides, and the receiver logic begins to search for the preamble. An abort also occurs if any data chip containing 0011, 1010, 0101, or 1001 occurs (invalid chips that do not occur in the stop flag).

The receive logic continuously searches for the 8-chip stop flag. Once it is recognized, the last byte that was placed within the receive FIFO is flagged as the last byte of the frame and the data in the temporary FIFO is removed and used as the 32-bit CRC value for the frame. Instead of placing this in the receive FIFO, the receive logic compares it to the CRC-32 value, which is continuously calculated using the incoming data stream. If they do not match, the last byte that was placed within the receive FIFO is also tagged with a CRC error. The CRC value is not placed in the receive FIFO.

If the user disables the HSSP’s receiver during operation, reception of the current data byte is stopped immediately, the serial shifter and receive FIFO are cleared, control of the RXD2 pin is given to the peripheral pin control (PPC) unit, and all clocks used by the receive logic are automatically shut off to conserve power. The user should ensure that the polarity of the RXD2 input is reprogrammed properly if this pin is to be used as a GPIO input.

11.10.2.9Transmit Operation

Before enabling the HSSP for transmission, the user may either “prime” the transmit FIFO by filling it with data or allow service requests to cause the CPU or DMA to fill the FIFO once the HSSP is enabled. Once enabled, the transmit logic issues a service request if its FIFO is empty. For each frame output, a minimum of 16 preambles are transmitted. If data is not available after the sixteenth preamble, additional preambles are output until a byte of valid data resides within the bottom of the transmit FIFO. The preambles are then followed by the start flag and then the data from the transmit FIFO. Four chips (8 bits) are encoded at a time and then loaded into a serial shift register. The contents are shifted out onto the TXD2 pin clocked by the 8-MHz baud clock. Note that the preamble, start and stop flags, and CRC value are automatically transmitted and need not be placed in the transmit FIFO.

When the transmit FIFO is emptied halfway, an interrupt and/or DMA service request is signalled. If new data is not supplied soon enough, the FIFO is completely emptied, and the transmit logic attempts to take additional data from the empty FIFO (one of two actions can be taken as programmed by the user). An underrun can either signal the normal completion of a frame or an unexpected termination of a frame in progress.

When normal frame completion is selected and an underrun occurs, the transmit logic transmits the 32-bit CRC value calculated during the transmission of all data within the frame (including the address and control bytes), followed by the stop flag to denote the end of the frame. The transmitter then continuously transmits preambles until data is once again available within the FIFO. Once data is available, the transmitter begins transmission of the next frame.

When unexpected frame termination is selected and an underrun occurs, the transmit logic outputs an abort and interrupts the CPU. An abort continues to be transmitted until data is once again available in the transmit FIFO. The HSSP then transmits 16 preambles, a start flag, and starts the new frame. The off-chip receiver can choose to ignore the abort and continue to receive data or signal the HSSP to retry transmission of the aborted frame.

SA-1100 Developer’s Manual 11-109