Intel SA-1100 manual Active Mode Pixel Clock and Data Pin Timing

Peripheral Control Module

Figure 11-14. Active Mode Pixel Clock and Data Pin Timing

L_FCLK
(VSYNC)
L_BIAS
OE)
L_LCLK
(HSYNC)
			PCP = 0
L_PCLK
	Data Pins Sampled					Data Pins Change
LDD[7:0],		by the Display
	Pixels 0 through 15 Pixels 16			through 31	Pixels 32 through 47 Pixels 48 through 63
GPIO[9:2]

Notes:

PCP - Pixel clock polarity:

0 - Pixels sampled from data pins on rising edge of pixel clock. 1 - Pixels sampled from data pins on falling edge of pixel clock.

A4794-01

SA-1100 Developer’s Manual 11-55