Coprocessors

5.2.3Register 2 – Translation Table Base

Register 2 is a read/write register that holds the base of the currently active level 1 page table. Bits <13:0> are undefined on read, ignored on write.

31

14

13

0

Translation Table Base

5.2.4Register 3 – Domain Access Control

Register 3 is a read/write register that holds the current access control for domains 0 to 15. Refer to the ARM Architecture Reference for a description of the domain structure

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

5.2.5Register 4 – RESERVED

Register 4 is reserved. Accessing this register yields unpredictable results.

5.2.6Register 5 – Fault Status

Reading register 5 returns the current contents of the fault status register (FSR). The FSR is written when a data memory fault occurs or can be written by an MCR to the FSR. It is not updated for a prefetch fault. See Chapter 7, “Memory-Management Unit (MMU)” for more details. Bits <31:10> are undefined on read, ignored on write. Bit 9 is set when a data breakpoint is taken and can be cleared by an MCR operation. Bit 8 is ignored on write and is always returned as zero. Refer to the ARM Architecture Reference for a description of the domain and status fields.

31

10

9

8

7

4

3

0

D 0 Domain

Status

5.2.7Register 6 – Fault Address

Reading register 6 returns the current contents of the fault address register (FAR). The FAR is written when a data memory fault occurs with the virtual address of the data fault or can be written by an MCR to the FAR.

31

0

Fault Virtual Address

5-4

SA-1100 Developer’s Manual

Page 48
Image 48
Intel SA-1100 manual Register 2 Translation Table Base, Register 3 Domain Access Control, Register 4 Reserved