Intel SA-1100 manual Caches, Write Buffer, and Read Buffer

Caches, Write Buffer, and Read Buffer

Any two data words with the same virtual address may not be contained in the RB at the same time. If an RB allocate references a data word that is already contained in another RB entry, then the old RB entry is invalidated and the new allocation is performed. It is possible for a portion of a cache clock at a given virtual address to be contained in one RB entry while another portion of the same block is contained in another RB entry. However, a given word can not be in more than one entry at a time.

If a load instruction misses in the RB, then a normal cache fill is performed (provided the cache is enabled and the page is marked cacheable). It then presents the possibility of having a partial line resident in the RB as well as having the line present in one of the Dcaches. This presents coherency issues that must be managed by software. If this situation does occur and the addressed data is in both the Dcache and the RB, then the data is sourced from the RB. If an RB entry contains a partial cache block (1 or 4 words), then those words will be sourced from the RB while the remaining words are sourced from the data cache or memory.

RB allocate instructions are not affected by the cache enable bit (bit 2 in the control register) or by the C bit in the MMU. Any RB allocate to a valid RB entry causes that RB entry to be invalidated, followed by a new allocation for the desired data. This occurs regardless of the address of the data currently in the buffer. For example, back-to-back RB allocate instructions to the same entry at the same address will invalidate the entry caused by the first instruction prior to performing the second fill.

An RB allocate or a load instruction that is issued to an RB entry currently being filled will stall until the fill completes. If a data abort is signaled on a read buffer allocate, the fill completes. After that, if a load to that entry is attempted, a data abort exception is issued. The coprocessor 15 register provides the ability to invalidate individual entries in the RB or to invalidate the entire buffer in one operation. RB coherency must be managed in software. Writes to addresses present in the read buffer are not written into the buffer. Specific RB entries must be invalidated before writing to the addresses or changing the page tables of the entries. Coherency is not checked between the RB and the WB. The WB should be drained prior to performing an RB load.

SA-1100 Developer’s Manual 6-7