Intel SA-1100 manual Uart Status Register

Peripheral Control Module

11.11.7UART Status Register 0

UART status register 0 (UTSR0) contains bits that signal the transmit FIFO interrupt request, receive FIFO interrupt request, receiver idle detect, the begin and end of receiver break detect conditions, and the error in receive FIFO condition. Each of these hardware-detected events signals an interrupt request to the interrupt controller.

Interruptible status bits signal an interrupt requested as long as the bit is set. Once the bit is cleared, the interrupt is cleared. Read/write bits are called status bits, read-only bits are called flags. Status bits are referred to as “sticky” (once set by hardware, must be cleared by software). Writing a one to a sticky status bit clears it; writing a zero has no effect. Read-only flags are set and cleared by hardware; writes have no effect. Additionally, some bits that cause interrupts have corresponding enable/mask bits in the control registers and are indicated in the following section headings. Note that the user has the ability to mask all UART interrupts by clearing bit 17 within the interrupt controller mask register (ICMR). See the Section 9.2, “Interrupt Controller” on page 9-11 .

11.11.7.1Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)

The transmit FIFO service request flag (TFS) is a read-only bit that is set when the transmit FIFO is nearly empty and requires service to prevent an underrun. TFS is set any time the transmit FIFO has four or fewer entries of valid data (half-full or less), and is cleared when it has five or more (more than half-full) entries of valid data. When the TFS bit is set, a DMA service request is made. An interrupt request is also made unless the transmit FIFO interrupt request mask (TIE) bit is cleared. After the DMA or CPU fills the FIFO such that five or more locations are filled within the transmit FIFO, the TFS flag (as well as the DMA and interrupt request) is automatically cleared.

11.11.7.2Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt)

The receive FIFO service request flag (RFS) is a read-only bit that is set when the receive FIFO is nearly filled and requires service to prevent an overrun. The amount of data that causes RFS to be set is nondeterministic. However, the range in which RFS will be set is guaranteed. RFS is set at some point when the receive FIFO is one- to two-thirds full (or more). The UART’s FIFOs are self-timed to reduce cost and save power. As a result, the depth at which the receive FIFO service request is generated is variable. This is the reason the receive FIFO is 12 entries deep instead of eight like the transmit FIFO. At which entry in the FIFO the request is actually triggered is dependent on IC process, operating temperature, and so on. The receive FIFO is designed to signal the RFS bit to be set when it contains eight entries of valid data. However, because of the variability of the self-timed logic, RFS may also be set when seven, six, or five entries of valid data are present within the FIFO. Likewise, under normal circumstances, RFS is cleared when the receive FIFO has seven remaining entries of valid data. However, again due to variations, RFS may be cleared when six, five, or four entries of data remain.

When the RFS bit is set, a DMA service request is made. An interrupt request is also made unless the receive FIFO interrupt request enable (RIE) bit is cleared. Even though more than four entries of data may exist within the receive FIFO, the user must configure the DMA burst size to 4 words. If programmed I/O is used to service the receive FIFO, a maximum of 4 words may be removed without checking if data is valid. After this point, the receive FIFO not empty (RNE) flag must be polled before each read to see if more data remains. After the DMA or CPU empties the FIFO such that five or more empty locations are available within the receive FIFO, the RFS flag (as well as the DMA and interrupt request) is automatically cleared.

SA-1100 Developer’s Manual 11-139