Intel SA-1100 manual DMA Buffer a Start Address Register DBSAn

Peripheral Control Module

The IE bit is the interrupt enable for the channel. An interrupt is generated if the DONEA, DONEB, or ERROR bits are set and the IE bit is set. The interrupt is negated when all of these status bits are cleared.

The ERROR bit is set if the DMA controller is incorrectly programmed and points to reserved memory space. No error is generated for references to nonexistent external memory. If enabled, ERROR generates a channel interrupt.

The DONEA bit is a status bit set by the DMA controller to indicate that the transfer to or from buffer A has completed. If enabled, DONEA causes a channel interrupt.

The STRTA bit is written by the user to start the channel transfer to or from buffer A. When DONEA is set, STRTA is cleared. The immediate action resulting from setting STRTA is dependent on the state of the BIU bit.

The DONEB bit is a status bit set by the DMA controller to indicate that the transfer to or from buffer B has completed. If enabled, DONEB will cause a channel interrupt.

The STRTB bit is written by the user to start the channel transfer to or from buffer B. When DONEB is set, STRTB is cleared. The immediate action resulting from setting STRTB is dependent on the state of the BIU bit.

The BIU bit indicates the current buffer-in-use (A or B). If BIU is a zero, buffer A is in use. If BIU is a one, buffer B is in use.The setting of DONEA or DONEB toggles the BIU bit. This bit is never cleared except on reset (either hardware, software, or sleep). For this reason, the processor must interrogate this bit before programming the channel for a new transfer. If both STRTA and STRTB are set at the same time, the first buffer serviced depends on the state of BIU.

11.6.1.3DMA Buffer A Start Address Register (DBSAn)

The DBSAn is a 32-bit read/write register that contains the starting memory address for buffer A. This register may be written only when STRTA is zero.

11.6.1.4DMA Buffer A Transfer Count Register (DBTAn)

The DBTAn is a 32-bit read/write register that contains the current transfer count in bytes for buffer A. This register may be written only when the STRTA bit for this channel is a zero. The following figure shows the format of this register; question marks indicate that the values are unknown at reset.

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Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Read								Reserved
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	?0	0
Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Read

Reserved

TCA	TCA	TCA	TCA	TCA
12	11	10	9	8

TCA	TCA	TCA	TCA	TCA	TCA	TCA	TCA
7	6	5	4	3	2	1	0

Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?

Bit	Name	Description
		Transfer count (buffer A).
0..12	TCA<12:0>	This field is a 13-bit value and contains the current transfer count (in bytes) for the transfer
		to or from buffer A. The maximum value programmed via this transfer count is 8 Kbyte.
13..31	—	Reserved. These bits are reserved and read as zeros. Writes to this field have no effect.

11-12 SA-1100 Developer’s Manual