Intel SA-1100 11.9.9 SDLC Status Register 1

SA-1100 Developer’s Manual 11-99
Peripheral Control Module
11.9.9 SDLC Status Register 1
SDLC status register 1 (SDSR1) contains flags and status bits that indicate when the receiver is
synchronized, the transmitter is active, that the transmit FIFO is not full, that the receive FIFO is
not empty, a transition has been detected on the receive line, and when an end of frame, CRC error,
or underrun error has occurred. All bits within SDSR1 are noninterruptible.
11.9.9.1 Receiver Synchronized Flag (RSY) (read-only, noninterruptible)
The receiver synchronized (RSY) flag is a read-only bit that is set when the receiver is synchronized
with the incoming data stream and is cleared when the receiver logic is in hunt mode (looking for a
flag to achieve bit and frame synchronization) or the receiver is disabled (RXE=0). This bit does not
request an interrupt.
11.9.9.2 Transmitter Busy Flag (TBY) (read-only, noninterruptible)
The transmitter busy (TBY) flag is a read-only bit that is set when the transmitter is actively
transmitting a frame (address, control, data, CRC, start, or stop flag) or an abort, and is cleared when
the transmitter is idle (transmitting flags that are not part of a frame) or the transmitter i s disabled
(TXE=0). This bit does not request an interrupt.
11.9.9.3 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)
The receive FIFO not empty flag (RNE) is a read-only bit that is set whenever the receive FIFO
contains one or more bytes of valid data and is cleared when it no longer contains any valid data. This
bit can be polled when using programmed I/O to remove remaining bytes of data from the receive
FIFO because DMA service and CPU interrupt requests are made only when 8, 7, 6, or 5 bytes reside
within the FIFO. Data remains after each service request as well as at the end of a frame. This bit does
not request an interrupt.
11.9.9.4 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)
The transmit FIFO not full flag (TNF) is a read-only bit that is set whenever the transmit FIFO
contains one or more entries that do not contain valid data and is cleared when the FIFO is
completely full. This bit can be polled when using programmed I/O to fill the transmit FIFO over
its halfway mark. This bit does not request an interrupt.
11.9.9.5 Receive Transition Detect Status (RTD) (read/write, noninterruptible)
The receive transition detect (RTD) status bit is set whenever the receiver is enabled (RXE=1) and a
transition is detected on the RXD1 pin (either rising or falling). This bit does not request an interrupt.
11.9.9.6 End of Frame Flag (EOF) (read-only, noninterruptible)
The end of frame flag (EOF) is set when the last byte of data within a frame (including aborted
frames) resides within the bottom entry of the receive FIFO.
The receive FIFO contains three tag bits (8, 9, and 10) that are not directly readable. The 8th bit is
set at the top of the FIFO whenever the last byte within a frame is moved from the receive serial
shifter to the top of the receive FIFO. This tag travels along with the last data value as it moves
down the FIFO. Each time a data value is transferred to the bottom of the FIFO (caused by a read of
the previous value), the state of the tag bit is moved from the FIFO to the EOF bit in the status