SA-1100 Developer’s Manual xix
10-5 DRAM Memory Size Options.............................................. ...........................1 0-14
10-6 DRAM Row/Column Address Multiplexing .................................................... 10-14
11-1 Peripheral Control Modules’ Register Width and DMA Port Size .................... 11-2
11-2 Peripheral Units’ Base Addresses...... ....... ...................................................... 11-3
11-3 Peripheral Units’ Interrupt Numbers ................................................................ 11-4
11-4 Dedicated Peripheral Pins............ ...... ....... ...... ................................................ 11-5
11-5 Peripheral Unit GPIO Pin Assignment....... ...................................................... 11-6
11-6 Valid Settings for the DDARn Register........... .............................................. 11-10
11-7 Color/Gray-Scale Intensities and Modulation Rates ...................................... 11-24
11-8 LCD Controller Data Pin Utilization................................................................ 11-27
11-9 LCD Controller Control, DMA, and Status Register Locations ...................... 11-50
11-10 USB Bus States......................................... .................................................... 11-57
11-11 Endpoint Field Addressing............................................................... ..............11-59
11-12 Host Device Request Summary..................................................................... 11-63
11-13 UDC Control, Data, and Status Register Locations......................... ..............11-78
11-14 UART Control, Data, and Status Register Locations.............................. .....11-102
11-15 SDLC Control, Data, and Status Register Locations ................................... 11-103
11-16 UART Control, Data, and Status Register Locations.............................. .....11-127
11-17 HSSP Control, Data, and Status Register Locations....................... ............11-127
11-18 Serial Port 3 Control, Data, and Status Register Locations............. ............11-145
11-19 MCP Control, Data, and Status Register Locations..................................... 11-183
11-20 SSP Control, Data, and Status Register Locations ..................................... 11-183
11-21 PPC Control and Flag Register Locations. .................................................. 11-193
12-1 SA-1100 DC Maximum Ratings....................................................... ................12-1
12-2 SA-1100 DC Operating Conditions.................................................. ................12-2
12-3 SA-1100 Power Supply Voltages and Currents with TQFP Package........... ...12-3
13-1 SA-1100 Output Derating ................................................................................ 13-1
13-2 SA-1100 AC Timing Table for AA and BA Parts..................................... .........13-4
14-1 SA-1100 Pinout – 208-Pin Quad Flat Pack ..................................................... 14-2
14-2 SA-1100 Pinout – 256-Pin Mini-Ball Grid Array ............................................... 14-4
16-1 SA-1100 Boundary-Scan Interface Timing ...................................................... 16-9