Intel SA-1100 Memory-Management Unit MMU, MMU Faults and CPU Aborts, Data Aborts, MMU Registers

Memory-Management Unit (MMU) 7

This chapter describes the memory-management functions.

7.1Overview

The Intel® StrongARM® SA-1100 Microprocessor (SA-1100) implements the standard ARM™ memory-management functions using two 32-entry fully associative translation buffers (TBs). One is used for instruction accesses and the other for data accesses. On a TB miss, the translation table hardware is invoked to retrieve the translation and access permission information. Once retrieved, if the entry maps to a valid page or section, then the information is placed into the TB. The replacement algorithm in the TB is round robin. For an invalid page or section, an abort is generated and the entry is not placed in the TB.

7.1.1MMU Registers

See Section 5.2, “Coprocessor 15 Definition” on page 5-2for a description of the Memory Management Unit (MMU) coprocessor 15 registers supported by the SA-1100.

7.2MMU Faults and CPU Aborts

The MMU generates four faults:

•Alignment fault

•Translation fault

•Domain fault

•Permission fault

Alignment faults are generated by word loads or stores with the low-order two address bits nonzero, and by load or store half words when the low-order address bit is a one. Translation faults are generated by access to pages marked invalid by the memory-management page tables. Domain faults and permission faults are generated by accesses to memory that are protected by the current mode, domain, and page protection. See the ARM Architecture Reference for more information. In addition, an external abort may be raised on external data accesses.

7.3Data Aborts

The SA-1100 takes a data abort exception due to: MMU-generated exceptions, accessing reserved memory space, and assertion of the abort pin while accessing expansion memory. Writes to memory areas marked as bufferable ignore the external abort pin.

SA-1100 Developer’s Manual 7-1