Intel manual Features of the SA-1100 CPU for AA and EA Parts

Introduction

Table 1-1. Features of the SA-1100 CPU for AA and EA Parts

•	High Performance	• 3.3 V I/O interface
	— 150 Dhrystone 2.1 MIPS @ 133 MHz	• 208-pin thin quad flat pack (LQFP)††
	— 220 Dhrystone 2.1 MIPS @ 190 MHz	• 256 mini-ball grid array (mBGA)
• Low power (normal mode)†		•	32-way set-associative caches
	— <230 mW @1.5 V/133 MHz		— 16 Kbyte instruction cache
	— <330 mW @ 1.5 V/200 MHz		— 8 Kbyte write-back data cache
•	Integrated clock generation	•	32-entry memory-management units
	— Internal phase-locked loop (PLL)		— Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte
	— 3.686 MHz oscillator	•	Write buffer
	— 32.768 kHz oscillator		— 8-entry, between 1 and 16 bytes each
•	Power-management features	•	Read buffer
	— Normal (full-on) mode		— 4-entry, 1, 4, or 8 words
	— Idle (power-down) mode	•	Memory bus
	— Sleep (power-down) mode		— Interfaces to ROM, Flash, SRAM,
• Big and little endian operating modes			and DRAM

— Supports two PCMCIA sockets

† Power dissipation, particularly in idle mode, is strongly dependent on the details of the system design.

††Package nomenclature has been modified due to industry standardization of packages. LQFP is 1.4mm thick, thin quad flat pack. Please note that no modification has been made to the package itself.

Table 1-2. Features of the SA-1100 CPU for CA and DA Parts

•	High Performance	• 256 mini-ball grid array (mBGA)
	— 180 Dhrystone 2.1 MIPS @ 160 MHZ	•	32-way set-associative caches
	— 250 Dhrystone 2.1 MIPS @ 220 MHz		— 16 Kbyte instruction cache
• Low power (normal mode)†			— 8 Kbyte write-back data cache
	— <430 mW @ 2.0-V/160-MHz	•	32-entry memory-management units
	— <550 mW @ 2.0-V/220-MHz		— Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte
•	Integrated clock generation	•	Write buffer
	— Internal phase-locked loop (PLL)		— 8-entry, between 1 and 16 bytes each
	— 3.686-MHz oscillator	•	Read buffer
	— 32.768-kHz oscillator		— 4-entry, 1, 4, or 8 words
• Big and little endian operating modes		•	Memory bus
•	3.3-V I/O interface		— Interfaces to ROM, Flash, SRAM,
• 208-pin thin quad flat pack (LQFP)††			and DRAM

— Supports two PCMCIA sockets

† Power dissipation, particularly in idle mode, is strongly dependent on the details of the system design.

††Package nomenclature has been modified due to industry standardization of packages. LQFP is 1.4mm thick, thin quad flat pack. Please note that no modification has been made to the package itself.

1-2 SA-1100 Developer’s Manual