Peripheral Control Module

Figure 11-12. Passive Mode Pixel Clock and Data Pin Timing

L_FCLK

L_LCLK

PCP = 0

L_PCLK

Data Pins Sampled by the Display

LDD[3:0]*

Pixels 0 through 3

Pixels 4 through 7

*DPD = 0

Data Pins Change

Pixels 8 through 11

Pixels 12 through 15

Notes:

PCP - Pixel clock polarity:

0 - Pixels sampled from data pins on rising edge of pixel clock. 1 - Pixels sampled from data pins on falling edge of pixel clock.

DPD - Dual pixel data mode:

0 - 4 data pins are used in single-panel monochrome mode. 1 - 8 data pins are used in single-panel monochrome mode.

A4792-01

SA-1100 Developer’s Manual

11-53

Page 203
Image 203
Intel SA-1100 manual Passive Mode Pixel Clock and Data Pin Timing, Dpd =