Intel SA-1100 9.5 Power Manager

9-26 SA-1100

Developer’s Manual

System Control Module

9.5 Power Manager

The SA-1100 contains power management logic that controls the transition between three different

modes of operation: run, idle, and sleep. These modes are used to reduce processor power

consumption at times when some functions are not needed, or when the system’s power supply is

low or out of regulation. Each of the respective modes is associated with a reduced level of power

consumption. Idle mode is entered via software. Sleep mode is entered either via software or by

asserting one of two input pins that indicate a power supply fault. Idle mode is exited through an

interrupt. Sleep mode is exited through a preprogrammed wake-up condition. Both modes may be

exited in extreme cases via hardware reset. If none of the power management modes is active and

the SA-1100 is out of reset, then it is said to be in run mode.

Run mode is the normal operating mode of the SA-1100: all power supplies are enabled, all clocks

are running, and every on-chip resource is functional. This is the normal state of operation for the

processor while it is executing code. Under usual conditions, the processor enters run mode after

successful power-up and reset of the part.

Idle mode allows a software application to stop the CPU when not in use, while continuing to

monitor interrupt service requests both on or off-chip. When an interrupt occurs, the CPU is

reactivated. During idle mode, the SCM, PM, and MPCM are each fully operational.

In idle mode, the CPU clock is stopped. Since the SA-1100 is static, all CPU state information is

saved. This allows the part to be switched back to run mode, starting operation exactly where it left

off. During idle mode, all other on-chip resources are active, including: all system unit modules

(real-time clock, operating system timer, interrupt controller, general-purpose I/O, and power

manager); all peripheral unit modules (DMA controller, LCD controller, serial controller 0-4); and

all memory controller resources. The PLL also remains in lock so that the part can be brought out

of idle mode quickly when an interrupt occurs.

Idle mode is entered while in run mode by executing a three instruction sequence consisting of the

privileged on-chip coprocessor 15 instruction ‘disable clock switching’, a load from a

noncacheable memory location (C=B=0), and the privileged on-chip coprocessor 15 instruction

‘wait for interrupt’. This sequence must reside in the first three words of an instruction cache line,

which requires that the linker align the idle mode instruction sequence on an eight word boundary.

Idle mode is entered by following the exact code sequence:

AREA  Idle$$Code , CODE, READONLY, ALIGN=5

;Aligned to 8 word boundary

;p15 = coprocessor 15

;r0 = register 0 (contents not used)

;c15 = test, clk, and idle cntl register

;c2 = CRm = 0b0010

mcr p15, 0, r0, c15, c2, 2 ;2 = OPC_2 = 0b010

ldr r0, <r1> ;<r1> points to non-cachable mem loc

mcr p15, 0, r0, c15, c8, 2 ;c8 = CRm = 0b1000