Intel manual Changes to the SA-1100 Core from the SA-110

Introduction

Table 1-3. Changes to the SA-1100 Core from the SA-110

• Data cache reduced from 16 Kbyte to		•	Hardware breakpoints
	8 Kbyte	• Memory-management unit (MMU)
•	Interrupt vector address adjust capability
			enhancements
•	Read buffer (nonblocking)	•	Process ID mapping

•Minicache for alternate data caching

Table 1-4. Additional Features Built into SA-1100 Chipset

•Memory controller supporting ROM, Flash, EDO, standard DRAM, and SRAM

•LCD controller

—1-, 2-, or 4-bit gray-scale levels

—8-, 12-, or 16-bit color levels

•Serial communications module supporting

SDLC

•230-Kbps UART

•Touch-screen, audio, telecom port

•Infrared data (IrDA) serial port

—115 Kbps, 4 Mbps

•Six-channel DMA controller

•Integrated two-slot PCMCIA controller

•Twenty-eight general-purpose I/O ports

•Real-time clock with interrupt capability

•On-chip oscillators for clock sources

•Interrupt controller

•Power-management features

—Normal (full-on) mode

—Idle (power-down) mode

—Sleep (power-down) mode

•Four general-purpose interruptible timers

•12-Mbps USB device controller

•Synchronous serial port (UCB1100, UCB1200, SPI, TI, Wire)

SA-1100 Developer’s Manual 1-3