Intel SA-1100 manual UDC Endpoint 2 Control/Status Register, Transmit Fifo Service TFS

Peripheral Control Module

11.8.9UDC Endpoint 2 Control/Status Register

The UDC endpoint 2 control status register contains 6 bits that are used to operate endpoint 2 (IN endpoint).

11.8.9.1Transmit FIFO Service (TFS)

The transmit FIFO service bit will be active if there are 8 or less (out of 16) bytes remaining in the transmit FIFO. This bit will be used as a DMA request to trigger the DMA unit to service the transmit FIFO.

11.8.9.2Transmit Packet Complete (TPC)

The transmit packet complete bit will be set by the UDC when an entire packet has been sent to the host. When this bit is set, the TIR bit in the UDC status/interrupt register will be set if transmit interrupts are enabled. This bit can be used to validate the other status/error bits in the endpoint 2 control/status register. The TPC bit gets cleared by writing a one to it. The UDC will issue NAK handshakes to all IN tokens while this bit is set.

11.8.9.3Transmit Packet Error (TPE)

The transmit packet error bit acts as a status bit and will be valid while TPC is set. The TPE bit being set will indicate that the host did not issue an ACK handshake to the current packet. The TPE bit will be cleared when the TPC bit is cleared.

11.8.9.4Transmit Underrun (TUR)

The transmit underrun bit will be set if the transmit FIFO experiences an underrun. This bit will be valid when the TPC bit is set. When the UDC experiences an underrun, the packet is shortened and the CRC is corrupted to ensure that the host discards the packet. The TUR bit will be cleared when the TPC bit is cleared.

11.8.9.5Sent STALL (SST)

The sent stall bit indicates that a STALL handshake was issued to the host. The CPU writes a one to this bit to clear it. When this bit is cleared the transmit FIFO is flushed.

11.8.9.6Force STALL (FST)

The CPU can set the force stall bit to force the UDC to issue a STALL handshake to all IN tokens. STALL handshakes will continue to be sent until the CPU clears this bit. The sent stall bit (4) will be set when the STALL state is actually entered (this may be delayed if the UDC is active when the FST bit is set), and the STALL state will not be exited until both the FST and SST bits are cleared.

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