Intel SA-1100 manual Sdlc Operation, Bit Encoding

Peripheral Control Module

Used as a UART, serial port 1 is identical to serial port 3. It supports most of the functionality of the 16C550 protocol including 7 and 8 bits of data (odd, even, or no parity), one start bit, either one or two stop bits, and transmits a continuous break signal. An interrupt is generated when a framing, parity, or receiver overrun error is present within the bottom four entries of the receive FIFO, when the transmit FIFO is half-empty or the receive FIFO is one- to two-thirds full, when a begin and end of break is detected on the receiver, and when the receive FIFO is partially full and the receiver is idle for three or more frame periods. Because programming and operation of serial port 1 as a UART is identical to serial port 3, see the Section 11.9, “Serial Port 1 – SDLC/UART” on page 11-78for a complete description of using serial port 1 in UART mode.

The external pins dedicated to this interface are TXD1 and RXD1. If serial transmission is not required and both the SDLC and UART are disabled, control of these pins is given to the peripheral pin control (PPC) unit for use as general- purpose input/output pins (noninterruptible). See the section 11.13 on page 184.

Modem control signals (RTS, CTS, DTR, and DSR) are not provided in this block but can be implemented using the general-purpose I/O port (GPIO) pins described in the Chapter 9, “System Control Module” .

11.9.1SDLC Operation

Following reset, both the SDLC and UART are disabled, which causes the peripheral pin controller (PPC) to assume control of the port’s pins. Reset causes the PPC to configure all of the peripheral pins as inputs, including serial port 1’s transmit ( TXD1) and receive (RXD1) pins. Reset also causes the SDLC’s transmit and receive FIFOs to be flushed (all entries invalidated). Before enabling the SDLC, the user must first clear any writable or “sticky” status bits that are set by writing a one to each bit. Next, the desired mode of operation is programmed in the control registers. At this point, the user can “prime” the transmit FIFO by writing up to eight values, or the FIFO can remain empty and either programmed I/O or the DMA can be used to service it after the SDLC is enabled. Once the SDLC is enabled, transmission and reception of data can begin on the transmit (TXD1) and receive (RXD1) pins.

11.9.1.1Bit Encoding

SDLC uses frequency modulation zero (FM0) to encode individual bits. Both the clock and the data are encoded and transmitted on the same line. Instead of representing data by controlling the state of the line, its frequency is used. The line transitions at a frequency that represents the serial stream’s bit rate (this produces the clock). Individual bits are separated by each transition. A zero is encoded by placing an extra transition at the middle of its bit period. A one is represented by no added transitions within its bit period (this produces the data). Note that nonreturn to zero (NRZ) bit encoding can also be programmed in the SDLC. In NRZ encoding, a one is represented when the line transitions, and a zero when the line does not transition. Figure 11-22shows both the NRZ and FM0 encoding of the data byte 8b 0100 1011. Note that the byte’s LSB is transmitted first.

SA-1100 Developer’s Manual 11-79