Intel SA-1100 Uart Register Definitions, Parity Enable PE, 11.11.3.2 Odd/Even Parity Select OES

Peripheral Control Module

removed from the receive FIFO without checking if more data is available. After this point, the user must poll a set of status bits that indicates if any data remains in the receive FIFO or if space is available in the transmit FIFO before emptying or filling the FIFOs any further.

11.11.1.6CPU and DMA Register Access Sizes

Bit positioning, byte ordering, and addressing of the UART is described in terms of little endian ordering. All UART registers are 8 bits wide and are located in the least significant byte of individual words. The ARM peripheral bus does not support byte or half-word operations. All reads and writes of the UART by the CPU should be wordwide. Two separate dedicated DMA requests exist for both the transmit and the receive FIFO. If the DMA controller is used to service the transmit and/or receive FIFOs, the user must ensure the DMA is properly configured to perform bytewide accesses, using 4 bytes per burst.

11.11.2UART Register Definitions

There are seven bytewide registers within the UART: four control registers, one data register, and two status registers. The control registers are used to program the baud rate, data length, number of stop bits, and odd or even parity. They are used to receive and transmit sample clock edge type, and to transmit a break. Also, they are used to enable or disable transmit and receive operation, parity, use of the sample clock input, and loopback mode. The data register is 8 bits and addresses the top location of the transmit FIFO and bottom location of the receive FIFO. When it is read, the receive FIFO is accessed, and when it is written, the transmit FIFO is accessed. The status registers contain bits that signal the transmit FIFO service request, receive FIFO service request, receiver idle, the begin and end of break detect, and error in FIFO conditions. Each of these status conditions signal an interrupt request to the interrupt controller. The status registers also flag when the UART is actively transmitting characters, when the transmit FIFO is not full, when the receive FIFO is not empty, and when a parity, framing, or overrun error was detected for the data value currently located in the bottom entry of the receive FIFO (no interrupt generated).

11.11.3UART Control Register 0

UART control register 0 (UTCR0) contains seven different bit fields that control various functions within the UART.

11.11.3.1Parity Enable (PE)

The parity enable (PE) bit is used to enable or disable parity checking by the receive data logic as well as parity generation by the transmit logic. When parity is enabled (PE=1), the odd/even parity select (OES) control bit is decoded to determine which type of parity should be checked and generated. The parity of each data frame received is checked. If the parity type programmed in the OES bit does not match the parity of the data received, the parity error (PRE) bit is set in the same entry in the receive FIFO where the errant data resides. When parity is disabled (PE=0), the parity check and generation logic is disabled, parity bits are not inserted into transmitted frames, and the receive logic expects a stop bit to occur after the MSB of each data value is received.

11.11.3.2Odd/Even Parity Select (OES)

The odd/even parity select (OES) bit is used to select whether odd or even parity should be used by the transmit and receive logic. When OES=0, odd parity is selected; when OES=1, even parity is selected. When parity is enabled (PE=1), the parity bit is placed after the data’s MSB in each frame.

SA-1100 Developer’s Manual 11-131