Intel SA-1100 Bit Modulation Select BMS, Sample Clock Enable SCE, Sample Clock Direction SCD

Peripheral Control Module

11.9.3.4Bit Modulation Select (BMS)

The bit modulation select (BMS) bit selects whether the SDLC uses NRZ or FM0 bit encoding for both transmit and receive data. When BMS=0, FM0 encoding is selected and when BMS=1, NRZ encoding is selected. In frequency modulation zero (FM0) encoding, a transition occurs on every bit boundary. Zeros are represented by an additional transition in the middle of the bit period, and ones are represented by the lack of an additional transition in the middle of the bit period. In nonreturn to zero (NRZ) encoding, a one is represented when the pin is high, and a zero when the pin is low. Note that bit-stuffing/bit-extraction (the insertion/deletion of a zero after five ones are encountered) is not affected by BMS. Also note that NRZ encoding must be selected (BMS=1) when sample clock operation is enabled (SCE=1).

11.9.3.5Sample Clock Enable (SCE)

The sample clock enable (SCE) bit is used to enable or disable driving or receiving a clock using GPIO pin 16 for synchronous transmission/reception of data. When SCE=0, the on-chip

3.6864-MHz PLL, the SDLC’s programmable baud rate generator, and the receive logic’s digital PLL are used. When SCE=1, the sample clock direction (SCD) bit is decoded to determine the direction of the clock used on GPIO pin 16.

11.9.3.6Sample Clock Direction (SCD)

When the sample clock function is enabled (SCE=1), the sample clock direction (SCD) bit is used to select whether the sample clock is an input from or an output to GPIO pin 16.

When SCD=0, the sample clock is input using GPIO pin 16 and is used to synchronously drive both the transmit and receive logic. For the receive logic, the RCE bit is decoded to select which edge of the input clock is used to latch each bit of the incoming frame. Note that the clock is not embedded within the data stream, and the digital PLL is shut down to conserve power. For the transmit logic, the TCE bit is decoded to select which edge of the input clock is used to drive each bit of the outgoing frame. The on-chip clock used to drive the programmable baud rate generator is shut down to conserve power. Note that input clock frequency to GPIO<16> cannot exceed 3.6864 MHz.

When SCD=1, the sample clock, which is generated within the SDLC unit (the clock that is output after dividing the 3.6864-MHz reference by the programmable BCD field, but before the fixed divide by 16), is output to GPIO pin 16, and again the RCE and TCE bits are decoded to determine which edge of this clock output is used to sample receive data and drive transmit data. Because the baud clock that is generated before the fixed divide by 16 is used to synchronously drive the SDLC, the effective baud rate is 16 times greater, allowing the SDLC to operate at speeds ranging from 899.78 bps to 3.6864 Mbps.

When the sample clock function is enabled (SCE=1), the user must program the SDLC bit modulation select (BMS) control bit to select NRZ encoding (BMS=1). Unpredictable results occur when FM0 encoding is selected during sample clock operation. Note that the SDLC frame format is not affected during sample clock operation, only the sampling and driving of individual data bits. Bit stuff (insertion of a zero after five consecutive ones) still occurs during NRZ encoding.

11-86 SA-1100 Developer’s Manual