10-2 SA-1100
Developer’s Manual
Memory and PCMCIA Control Module
4 byte selects, nCAS<3:0>, 12 bits of multiplexed row and column addresses, nWE, and nOE. The
SA-1100 performs CAS before RAS refresh (CBR) during normal operation and supports
self-refreshing DRAMs during power-down sleep mode.
•Static Memory Interface
The static memory interface has four chip selects, nCS<3:0>, and 26 bits of byte address, A<25:0>,
for access of up to 64 Mbyte of memory in each of four banks. Each chip select is individually
programmable for selecting nonburst ROM, burst ROM, Flash EPROM, or asynchronous SRAM.
Each may be individually configured to be 16 or 32 bits wide except SRAM, which, if used, must
be 32 bits. nOE is asserted on reads and nWE is asserted on writes. For SRAMs, nCAS<3:0> are
byte selects for both reads and writes. Because the nCAS<3:0> pins are used to control both
SRAM and DRAM, systems with both memory types are not supported.
When the SA-1100 comes out of reset, it begins fetching and executing instructions at address
0x00, which corresponds to memory selected by nCS0. This is where boot ROM is expected to be.
•PCMCIA Interface
The PCMCIA interface provides control signals to support a single PCMCIA card slot with
additional hooks to support two slots. It shares address and data pins with the memory devices. It
uses address lines, A<25:0>, and data lines, D<15:0>. nPREG is actually A<26> and selects
register space (I/O or attribute) versus memory space. nPOE and nPWE are provided for memory
and attribute reads and writes. nPIOR, nPIOW, and nIOIS16 control I/O reads and writes.
nPWAIT allows for extended access times. nPCE1 and nPCE2 are byte select low and high,
respectively. PSKTSEL selects between two card slots.
This interface also supports 32-bit accesses that are outside the PCMCIA specification. There are
several restrictions with respect to the use of this feature that are described later in this chapter.