Intel SA-1100 manual Reviving the DRAMs from Self-Refresh Mode, Memory and Pcmcia Control Module

		9.5.3.6	Booting After Sleep Mode	9-29
		9.5.3.7 Reviving the DRAMs from Self-Refresh Mode		9-30
	9.5.4	Notes on Power Supply Sequencing		9-30
	9.5.5	Assumed Behavior of an SA-1100 System in Sleep Mode		9-30
	9.5.6	Pin Operation in Sleep Mode		9-32
	9.5.7	Power Manager Registers		9-33
		9.5.7.1 Power Manager Control Register (PMCR)		9-33
		9.5.7.2	Power Manager General Configuration Register (PCFR)	9-34
		9.5.7.3 Power Manager PLL Configuration Register (PPCR)		9-35
		9.5.7.4 Power Manager Wake-Up Enable Register (PWER)		9-36
		9.5.7.5 Power Manager Sleep Status Register (PSSR)		9-37
		9.5.7.6 Power Manager Scratch Pad Register (PSPR)		9-39
		9.5.7.7 Power Manager GPIO Sleep State Register (PGSR)		9-39
		9.5.7.8	Power Manager Oscillator Status Register (POSR)	9-40
	9.5.8	Power Manager Register Locations		9-40
9.6	Reset Controller			9-41
	9.6.1	Reset Controller Registers		9-42
		9.6.1.1	Reset Controller Software Reset Register (RSRR)	9-42
		9.6.1.2	Reset Controller Status Register (RCSR)	9-43
	9.6.2	Reset Controller Register Locations		9-43
10		Memory and PCMCIA Control Module		10-1
10.1	Overview of Operation			10-1
	10.1.1	Example Memory System		10-3
	10.1.2	Types of Memory Accesses		10-4
	10.1.3	Reads	.................................................................................................	10-4
	10.1.4	Writes	................................................................................................	10-4
	10.1.5	Transaction Summary		10-4
	10.1.6	Read-Lock-Write		10-5
	10.1.7 Aborts and Nonexistent Memory			10-5
10.2	Memory Configuration Registers			10-6
	10.2.1	DRAM Configuration Register (MDCNFG)		10-7
	10.2.2	DRAM CAS Waveform Shift Registers
		(MDCAS0, MDCAS1, MDCAS2)		10-9
	10.2.3	Static Memory Control Registers (MSC1–0)		10-10
	10.2.4	Expansion Memory (PCMCIA) Configuration Register (MECR)		10-12
10.3	Dynamic Interface Operation			10-14
	10.3.1	DRAM Overview		10-14
	10.3.2	DRAM Timing		10-15
	10.3.3	DRAM Refresh		10-18
	10.3.4	DRAM Self-Refresh in Sleep Mode		10-18
10.4	Static Memory Interface			10-18
	10.4.1	ROM Interface Overview		10-19
	10.4.2	ROM Timing Diagrams and Parameters		10-19
	10.4.3	SRAM Interface Overview		10-22
	10.4.4	SRAM Timing Diagrams and Parameters		10-22
	10.4.5 FLASH EPROM Interface Overview			10-23
	10.4.6 FLASH EPROM Timing Diagrams and Parameters			10-24
10.5	General Memory BUS Timing			10-25
	10.5.1	Static Access Followed by a DRAM Access		10-25
	10.5.2	DRAM Access Followed by a Static Access		10-25

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