Intel SA-1100 manual Initialization of the Memory Interface, 10-34

Memory and PCMCIA Control Module

10.7Initialization of the Memory Interface

On power-on reset, the dynamic memory interface is disabled and the static interface for the boot ROM, connected to nCS0, is configured for the slowest nonburst ROM/Flash EPROM. The ROM_SEL pin determines the bus size of the boot ROM (nCS0).

Initialization software is responsible for setting up the memory interface configuration registers before enabling the DRAM interface by setting MDCNFG:DE3-0.

Most DRAMs require a wait period followed by a series of refresh cycles before the first memory access. The SA-1100 provides a mechanism for software to control these events. When a particular DRAM bank (bank n, selected by nRAS) is disabled (MDCNFG:DEn=0), a read from any address in that bank will trigger a CBR refresh cycle for all banks.

10.7.1Flow of Events After Reset or Exiting Sleep Mode

On power-on reset, the memory controller is in the following state: nRAS(3:0) = 0xF

nCAS(3:0) = 0xF nCS(3:0) = 0xF nOE = 1

nWE = 1 nPIOR = 1 nPIOW = 1 nPOE = 1 nPWE = 1

All DRAM banks disabled (MDCNFG:DE3:0 = 0).

Static interface set to slowest nonburst ROM/Flash timing.

(MSC0:SMCNFG0 field is initialized as follows:

RRR=0xF, RDN=0x1F, RDF=0x1F, RBW = not ROM_SEL, RT=0)

Upon exiting sleep mode, the memory controller is in a state similar to reset, except the nCAS and nRAS pins remain asserted to ensure that the DRAMs remain in a self-refresh state until the processor has been configured:

nRAS(3:0) = 0 nCAS(3:0) = 0 nCS(3:0) = 0xF nOE = 1 nWE = 1 nPIOR = 1 nPIOW = 1 nPOE = 1 nPWE = 1

All DRAM banks disabled (MDCNFG:DE3:0 = 0).

Static interface set to slowest nonburst ROM/Flash timing. (MSC0:SMCNFG0 field is initialized as follows:

RRR=0xF, RDN=0x1F, RDF=0x1F, RBW = not ROM_SEL, RT=0)

10-34 SA-1100 Developer’s Manual