Intel SA-1100 13.6.1 Asynchronous Signal Timing Descriptions

SA-1100 Developer’s Manual 13-5
AC Parameters
13.6.1 Asynchronous Signal Timing Descriptions
nPWAIT is an input and is received through a synchronizer. As such, it has no setup and hold
specification. The user must adhere to the protocol definition.
When the peripheral pins are in GPIO mode, they are read or written under software control. As
outputs, they are driven valid on the pin approximately 20 ns after they are written by software.
When inputs, they are received by a synchronizer and must be valid for approximately 20 ns before
they are able to be recognized by a CPU read.
nRESET must remain asserted for 150 ms after VDD and VDDX are stable to properly reset the
SA-1100.
nRESET_OUT is asserted for all types of reset (hard, watchdog, sleep, and software) and appears
on the pin asynchronously to all clocks.
BATT_FAULT and VDD_FAULT are asynchronous inputs and are synchronized to the
32.768-kHz clock after entering the SA-1100. They must be valid for approximately 60 ms before
they are recognized by the SA-1100.
PWR_EN asserts when the SA-1100 enters sleep mode and is driven onto the pin following the
rising edge of the 32.768-kHz clock. It negates on the same edge as sleep mode is exited.
GP<27:0> are read and written under software control. In addition, an asynchronous edge detect
may be performed. When writing a value to these pins, the pin transitions approximately 20 ns after
the write is performed. When reading these pins, the signal is first synchronized to the internal
memory clock and must be valid for at least 20 ns before it is visible to a processor read. For edge
detects, the value on the pin following an edge must be stable for at least 10 ns for the edge to be
caught by the edge detect circuit.
UDC+, UDC-, TXD_1, RXD_1, TXD_2, RXD_2, TXD_3, and RXD_3 are asynchronous relative
to any device outside the SA-1100. The output pins, like all outputs on the SA-1100, have been
characterized while driving a 50-pF lumped load capacitance.