Peripheral Control Module

Bit

Name

 

Description

 

 

 

6

TTU

Telecom transmit FIFO underrun.

 

 

0

– Telecom transmit FIFO has not experienced an underrun.

 

 

1

– Telecom transmit logic attempted to fetch data from transmit FIFO while it was

 

 

empty, request interrupt.

 

 

 

7

TRO

Telecom receive FIFO overrun.

 

 

0

– Telecom receive FIFO has not experienced an overrun.

 

 

1

– Telecom receive logic attempted to place data into receive FIFO while it was full,

 

 

request interrupt.

 

 

 

8

ANF

Audio transmit FIFO not full (read-only).

 

 

0

– Audio transmit FIFO is full.

 

 

1– Audio transmit FIFO is not full.

 

 

 

9

ANE

Audio receive FIFO not empty (read-only).

 

 

0

– Audio receive FIFO is empty.

 

 

1

– Audio receive FIFO is not empty.

 

 

 

10

TNF

Telecom transmit FIFO not full (read-only).

 

 

0

– Telecom transmit FIFO is full.

 

 

1

– Telecom transmit FIFO is not full.

 

 

 

11

TNE

Telecom receive FIFO not empty (read-only).

 

 

0

– Telecom receive FIFO is empty.

 

 

1

– Telecom receive FIFO is not empty.

 

 

 

12

CWC

Codec write completed (read-only).

 

 

0 – A write to a codec register has not completed since the last time this bit was cleared.

 

 

1

– A write to a codec register has been transmitted and has updated the register.

 

 

 

13

CRC

Codec read completed (read-only).

 

 

0

– The value read from the addressed codec register has not been returned to

 

 

MCDR2.

 

 

1

– The value read from the addressed codec register is now in MCDR2.

 

 

 

14

ACE

Audio codec enabled (read-only).

 

 

0

– The audio codec input and output is disabled (bits 14 and 15 are 0 in Audio Control

 

 

Reg B).

 

 

1

– Audio codec input and/or output is enabled (bits 14 and/or 15 is 1 in Audio Control

 

 

Reg B).

 

 

 

15

TCE

Telecom codec enabled.

 

 

0

– The telecom codec input and output is disabled (bits 14 and 15 are 0 in Telecom

 

 

Cntl Reg B).

 

 

1 – Telecom codec input and/or output is enabled (bits 14 and/or 15 is 1 in Telecom Cntl

 

 

Reg B).

 

 

 

31..16

Reserved.

 

 

 

 

11-168

SA-1100 Developer’s Manual

Page 318
Image 318
Intel SA-1100 manual Ttu, Tro, Anf, Ane, Tne, Cwc, Crc, MCDR2, Ace