OPERATING PRINCIPLES
2.3.5 PF Motor Drive Circuit
Stepping motor driver STK6713BMK4 (IC2) drives the PF motor. Figure
| Table |
Specification | Description |
Form | |
Supply Voltage | 37 VDC (applied to the drive circuit) |
Internal Coil Resistance | 2.8 ohms + 10 % per phase at 25 oC |
Frequency | 4274 pps** (normal mode,, constant driving): 9.9 ips*** |
| 2610 pps (middle speed mode,, constant driving): 6 ips |
Current Consumption | Driving: 1.75 A, + 0.20 A per phase (average) |
| Holding: 0.26 A, + 0. 2 A per phase (average) |
*HB …. Hybrid |
|
**pps …. pulses per second |
|
***ips …. inches per second |
|
The motor pulse switching signals are transmitted from CPU ports PG00 to PG03. The PF motor is controlled using
‰Micro feed (adjust) mode ‰Middle speed mode: ‰Normal speed mode:
:< 20 / 432 inches
>20 / 432 inches and < 60 / 432 inches, or with optional pull tractor
>60 / 432 inches
Each phase switching FET in driver IC2 is an open collector. When the phase switching data is HIGH, the motor is turned on. The PFA port of the gate array monitors the phase A signal of the PF motor and checks whether it is operating normally. The PFA port is used as the WDT (watch dog timer).
If PF motor operation is abnormal, the gate array outputs the /RSTOUT (reset request) signal to the system reset IC (IC13). Refer to Section 2.3.2 Reset Circuit.
Gate Array E05B36 (IC1)
MAIN Board
DRV
Board
+5V
PFH/R
PFA 
Ref. Voltage
Setting Circuit (Q9)
Vref
4.3 VDC
CPU TMP95C061A (IC2)
PG00
PG01
PG02
PG03
VREF |
| VREF |
IN_A | STK6713B | |
INXA |
| (IC2) |
IN_B |
| OUT_A |
INXB |
| OUTXA |
|
| |
|
| OUT_B |
SG | GP | OUTXB |
| ||
GP3
VP3
PF COM
PF A
PF B
PF C
PF D
GP3
Figure 2-23. PF Motor Drive Circuit Block Diagram
Rev. B |
